A Test Program Fault Simulator for Microprocessor SoftwareBased SelfTesting

1
A Test Program Fault Simulator for
Microprocessor Software-Based Self-Testing

• Advisor ????? Jiun-Lang Huang
• Presenter ??? Jiang-Jung Wu
• Date January 27, 2005
• Graduate Institute of Electronics Engineering
• National Taiwan University
• Taipei 106, Taiwan

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Introduction (1/2)

• BIST or scan chain insertion can provide higher
  fault coverage for complex SoC design, but two
  issues should be solved
• Higher power consumption.
• Area overhead.
• Software self-testing utilizes the instruction
  sets provided by a microprocessor
• To test structural faults without high power
  consumption and area overhead.
• This thesis presents a high accuracy fault
  simulator for given test programs and testbench
• To evaluate fault coverage and record fault
  dictionary.
• A validation flow to prove the correctness of
  fault simulator.

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Self-Test Methodology Flow
RTL files
Test program
Gate-level netlist
Assembler
Input files
Machine codes
Logic simulation
Waveforms and dumped Top-level signals
Tech file
Fault simulator
Translation tool
Fault dictionary
Fault coverage
Test file (STIL)
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Proposed Translation Method and Validation Flow

• Proposed translation method
• To translate the dumped top-level signals into
  test vectors.
• Considering the varies with different design and
  testbench, two rules have been set.
• A validation flow is developed for the proposed
  translation method.

Waveforms and dumped signals
RTL files
Logic simulation
Rule 1 Rule 2
Machine codes
Translation tool
Validation flow
Test file (STIL)