On Designing ViaConfigurable Cell Blocks for Regular Fabric

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On Designing Via-Configurable Cell Blocks for
Regular Fabric

• Yajun Ran
• Malgorzata Marek-Sadowska
• Department of Electrical and Computer Engineering
• University of California, Santa Barbara

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Standard-Cell and FPGAs

• High performance, small area, low power
  consumption
• Huge development and mask cost, long turn-around
  time
• Design rule, manufacturability

• Easy to design and debug, fast time-to-market
• Low performance, large area, high power
  consumption
• High unit cost

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Structured ASICs - Filling in the gap

• Give up field programmability
• Mask programmable
• Discard active switches
• Many parts pre-fabricated
• Pre-fabricated transistors
• Fixed lower-level interconnect
• Via-programmable fabric
• Customized via masks

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Via-Patterned Gate Array (VPGA)

• Patel et al. An architectural exploration of via
  patterned gate arrays, ISPD03

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Hybrid Cell Block
D
CK

• Pileggi et al. Exploring Regular Fabrics to
  Optimize the Performance Cost Trade-Off, DAC03

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Our Via-Configurable Cell (VCC)
Vdd
P-diff
N-diff
Poly
M1
M2
Contact
Gnd
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Cell function and layout
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VCC-realizable function enumeration
M
M
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Functional coverage of n-VCC

• Z. A. Lomnicki, Two-Terminal Series-Parallel
  Networks, Advances in Applied Probability, 1972

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Intra-cell wire requirement
8-VCC N(P)-part

• M2 rows required is 2(?(n-1)/2?2)

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Wire segmentation
8-VCC N-part
x1 x2 x3 x4 x5 x6 x7 x8
Example f (x1x2x3)(x4x5x6(x7x8))
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Wire segmentation
8-VCC N-part
x1 x2 x3 x4 x5 x6 x7 x8
Example f (x1x2x3)(x4x5x6(x7x8))
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Multiple-Gate Implementation
vdd
gnd
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Via-Decomposable DFF
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Via-Configurable MUX21
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Via-Configured Sizable Repeater Array
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Via-Configured Sizable Repeater Array
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Experimental setting

• Single block type
• 20 Largest MCNC benchmarks (2k 14k)
• FF 0 1.5k

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Evaluation flow

• Synthesis and mapping
• Greedy packing
• Block-level placement (Capo)
• Standard-cell-like global routing

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Experimental Results - Area
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Experimental Results - Delay
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Experimental Results Power consumption
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Experimental Results - Transistor utilization
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Conclusions Future work

• Via-configurable cell
• Compact layout
• Strong functional expression
• Fast and less power-consuming
• Via-decomposable FF
• Can be configured into combinational gates
• Improves cell utilization
• Future work
• Fixed routing structure
• Fabric-specific design flow

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Thank you!