AMS2 JCrate TopLevel DAQ Computer Status at CSIST

1
AMS-2 J-Crate (Top-Level DAQ Computer) Status
at CSIST

• Wei-Ping, Yang -CSIST
• Mar.1Mar. 4, 2005

2
J-Crate Architecture
4 independent JMDC (Main DAQ Computer)
2 independent optical output channels (JHIF)
2 independent 1553 terminal channels (JLIF)
AMS Specific Back plane (JBP)
3
J-Crate Design Flow
System specification and Architecture Design
PDR CDR
EM production
Component survey Prototype circuit design
TAAF FMEA
QM Production
EQT ESS EMI TVT
FM and FS Production
ESS TVT
TAAF Test,Analysis and Fix FMEA Failure Mode
Effect Analysis EQT Environmental Qualification
Test ESS Environmental Stress Screen TVT
Thermal Vacuum Test PIT Preliminary Interface
Test FIT Functional Interface Test
4
JSBC QM2 V2 Implementation
Remove old heat sink

• Cleaned previous thermal glue and added new
  thermal glue

Put new heat sink and fastening
5
JBU firmware DMA Implementation

• First version released in Oct.
• In Nov. meeting the designer has discussed with
  Dr. Kounine and understand the problems.
• The designer worked for this problem till end of
  Dec. but not successfully.
• Some problems have been solved, the rest problem
  is JSBC accessed the JBU register during DMA
  transfer may cause JBU hang.
• The reason cause this problem
• In order to meet the timing specification of
  SDRAM refresh operation, the JBU DMA operation
  has been divided into several sub-segments
  operations. After the transfer of each
  sub-segments the state machine may release the
  usage of BUS. Any access to JBU FPGA register may
  cause the state machine mal-function.
• The designer will continue to solve this problem
  from Mar. 1.
• Suggest make the decision in end of Mar. whether
  we need this function or not.

6
J-Crate FM design (I)

• JSBC
• Circuit , layout and components same as QM2 V2
• JBU
• Components same as QM2
• Circuit revised (remove unused test points and
  pin header)
• JIM-HRDL/422
• Components same as QM2
• Circuit revised (connect FPGA unused pins to
  ground)
• JIM-AMSW/1553
• Components same as QM2
• Circuit revised ( change resistors value and part
  no. of LVDS receiver)
• JIM-CAN
• Components same as QM2
• Circuit revised (remove unused test points)

7
J-Crate FM design (II)

• JHIF
• Circuit and components same as QM2
• Modify the front panel drawing
• JLIF
• Circuit , layout and components same as QM2
• JBP
• Circuit , layout and components same as JBP-F5
• Common CompactPCI connectors used press-in
  method layout rules

8
Quantities of Boards to be Produced

• JSBC 4 (FM) 4 (FS) 2 (ACOP EM), use flash
  and left RRHROMFPGA areas uncoated
• JBU 4 (FM) 4 (FS), left FPGA area uncoated
• JIM-CAN 4 (FM) 4 (FS), use RH
  micro-controller, flash area with socket and left
  RRHROMFPGA areas uncoated
• JIM-AMS/1553 4 (FM, with BU-61582 and BU-61580)
  2 (FS, with BU-61582) 2 (FS, without 1553
  chips), left FPGA areas uncoated
• JIM-HRDL 4 (FM) 4 (FS), left FPGA area
  uncoated
• JHIF 1 (FM) 2 (FS)
• JLIF 1 (FM) 2 (FS)
• JBP 1 (FM) 2 (FS)

9
Summary of J-Crate Status
10
Crate Assembly Process

• Conclusion from QM test A procedure should be
  defined for crate assembly and the test after
  crate assembled to reduce the clean steps before
  thermal vacuum test.
• For facility cleanliness consideration
• Crate assembly will be carried out in Building
  307
• Inspected by CSIST QC people
• Parts need to be cleaned before assembly
• All screws and washers
• Crate wall and other mechanical parts
• Assembly tools
• Cables and fixture for test support
• Touch the boards and crates must wear gloves

11
JJTJPD schedule

• Production
• J FM/FS module production Mar.1 Apr.30
• JT FM/FS module prod. Finished on Feb.28
• JPD FM/FS module prod. Finished on Jan. 31
• JJTJPD Crate mech Expected on Feb. 28
• Integration Test
• J, JT, JPD Crate ESS Jun. 1- Aug.31
  TBD
• J, JT, JPD Crate EMI To be Discussed
• JJTJPD Crate TVT Plan in Sep.
• JJTJPD Crate delivery To be specified

12
J-Crate ESS Schedule

• Base on the following considerations
• Board level test should be finished before May.
  31
• Need MIT people to perform integration and test
• Two crates need to be test in separate
• Three options
• After Next TEM in Taiwan from Jul. to Aug.
• Before Sep. TVT Test
• After FPGA firmware frozen (same as JT)