Dynamic Platform Management for Configurable PlatformBased SystemonChips

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Dynamic Platform Management for Configurable
Platform-Based System-on-Chips

• Krishna Sekar, Kanishka Lahiri, Sujit Dey

Mobile Embedded Systems Design Test
Lab, Dept. of ECE, University of California, San
Diego
NEC Laboratories America, Princeton, NJ
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Outline

• Configurable-Platform Based Design
• Dynamic Platform Management
• Platform Management Case Study
• Platform Management Methodology
• Experimental Results
• Conclusions and Future Work

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Configurable Platform-Based Design
General-Purpose Processors

• Higher performance, lower power, limited
  flexibilty
• Large platform development effort
• Need to develop extensive SW infrastructure
• Need to sell in volume to justify development cost

General Purpose Configurable Platforms
Improving flexibility, time-to-market, engg.
cost, time-in market,
Domain Specific Platforms
ASIC, Custom SoC
Improving performance, power, size
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Dynamic Platform Management

• Software layer for run-time, application-specific
  customization of multiple platform
  components/parameters
• Design techniques for integrated dynamic
  configuration of platform memory and
  frequency/voltage

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Static Configurability

• Statically Configurable Platform Components
• Processors with configurable instruction sets,
  data paths
• Tensilica Xtensa, Altera NIOS, Triscend E5
  processors
• Caches with configurable size, associativity
• MIPS32 4KE processor family
• Bus architectures with configurable width,
  arbitration
• ARM AMBA bus, IBM CoreConnect
• Static Customization Techniques
• Platune, Givargis, Vahid et al (TCAD 2002)
• PICO, Kathail et al (IEEE Computer 2002)
• Processor customization, Sun et al, Cheung et al,
  (ICCAD 2003)

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Emergence of Dynamic Configurability

• Dynamically configurable platform components
• Configurable processors with DVS
• Intel XScale, Transmeta Crusoe, AMD K6-III
  processors
• Configurable cache and memory architectures
• Motorola MCORE M340 processor
• Adaptive on-chip communication architectures
• Sonics SiliconBackplane, ARM AMBA, IBM
  CoreConnect
• On-chip configurable fabrics
• Altera Excalibur SOPC, Xilinx Virtex-II Pro,
  Elixent D-Fabrix
• Dynamic configuration techniques
• DVS techniques
• Cache and memory management techniques

Dynamic Platform Management Holistic approach
for simultaneous configuration of multiple
platform components
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Outline

• Configurable-Platform Based Design
• Dynamic Platform Management
• Platform Management Case Study
• Platform Management Methodology
• Experimental Results
• Conclusions and Future Work

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Case Study UMTS/WLAN Security Protocol Processing

• Dual access UMTS and IEEE 802.11b converged
  handset
• UMTS security processing task consists of
• Ciphering (f8)
• Integrity (f9)
• WLAN security processing task consists of
• Ciphering (WEP)
• Integrity (CRC)

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General Purpose Configurable Platform
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Benefits of Dynamic Platform Management
5114 bit frames, Type signalling, 1.8 Mbps
5114 bit frames, Type signalling, 384 Kbps
5114 bit frames, Type signalling, 200 Kbps
UMTS
2304 byte frames, Type encrypted, 6 Mbps
2304 byte frames, Type encrypted, 14 Mbps
2304 byte frames, Type encrypted, 11 Mbps
WLAN
Case 1
Case 2
Case 3
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Dynamic Platform Management Methodology
Application/protocol tasks
1. Memory access characterization
2. CPU cycles characterization
Off-line task characterization
1. On-chip memory configuration
2. Memory-aware frequency and
voltage selection
Run-time platform management
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Off-line Characterization Phase

• Off-line characterization of application/protocol
  tasks
• Data items accessed by tasks
• Maximum data item sizes
• Parameterized models of data item accesses
• Parameterized models of computation requirements
• Models constructed using combination of analysis
  and simulation (manual)

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Dynamic On-Chip Memory Configuration
Configurable Platform Architecture
External Memory
StrongARM1
Instruction Cache
Data Memory
data items
1
2
3
4
5

• Optimal memory configuration, Don, is that which
• Maximizes
• Constraint fit in on-chip memory

• Run-time estimation of accesses per data item
  using parameterized models
• Data selection problem NP-complete (0-1 Knapsack)
• Greedy heuristic algorithm used

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Memory-Aware Frequency and Voltage Setting

• Execution time for each task estimated by

On-chip memory access
External memory access
Computation

• Frequency is selected such that tasks just meet
  their deadlines

• Corresponding voltage level selected via lookup

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Experimental Methodology
UMTS WLAN code
UMTS WLAN code
Analysis cycle accurate simulation (ARMulator)
Compilation Optimization (armcc)
binary
Application instrumentation
Statically Optimized Platform On-chip memory
StackUMTS, KSUMTS, S7UMTS,StackWLAN,S-TableWLAN
Frequency/Voltage 206MHz, 1.5V
Compilation Optimization (armcc)
binary
Dynamic Platform Management Based
Architecture On-chip memory, frequency/ voltage
decided at run-time

• Performance/CPU load estimation cycle-accurate
  ISS (ARMulator)
• Power estimation cycle-accurate, software energy
  profiling (JouleTrack)
• Platform configuration overheads (i)
  frequency/voltage (from processor data) (ii)
  memory configuration (from cycle accurate
  simulation)

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Experimental Results Performance Impact
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Improvements in CPU Availability

• Platform Management helps improve CPU
  availability
• Freed CPU cycles can be exploited to
• Run other application/protocol tasks
• Save energy through aggressive frequency/voltage
  scaling

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Improvements in Energy Consumption

• Workload
• uniformly distributed frame sizes
• random frame types

2500
WLAN
2000
UMTS
13 Mbps
11 Mbps
14 Mbps
1500
1000
Frame Size (bytes)
384 Kbps
2 Mbps
5 Mbps
500
0
0.00
20.00
40.00
60.00
80.00
100.00
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Conclusions and Future Work

• Described design techniques for dynamically
  customizing a general-purpose configurable
  platform
• Dynamic platform management helps combine
  benefits of general-purpose application-specific
  approaches
• Compared to statically optimized designs,
  proposed approach enables
• Improved application performance
• More efficient platform resource usage
• Improved energy efficiency

• Future Work
• Extension to additional configurable platform
  components
• Demonstration on commercial configurable platform