Virtual Memory 15213-S04, Recitation, Section A

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Virtual Memory15213-S04, Recitation, Section A

• Exam 2 Issues
• Virtual Memory
• Cache structure

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Exam 2

• Times
• This Thursday, 9pm
• Review Session This Tuesday
• Topics
• Virtual Memory
• Cache Structure
• System I/O
• Exceptional Control Flow
• Signals
• Linking
• Cache Performance

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Cache Structure Performance

• Set size, line size (block size)
• Physical address is split to 3 parts for cache
• One cache miss will trigger a size of memory
  being fetched
• Eg line size 32 bytes, sequentially reading a
  large char array will have cache miss rate .
• Direct-mapped, N-way associative
• In directed-mapped, reading two different
  addresses with the same set index will
• In 2-way associative, reading two different
  addresses with the same set index will

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System I/O

• How many structures are involved in the file
  handling?
• What are the two main ways of sharing file? Any
  difference?

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Exception Control Signaling

• fork(),
• waitpid(),
• execve(),
• kill(),
• signal(),
• (textbook!)

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Linking

• Linker Symbol Rule?
• Strong and weak symbols?
• Shared Library, Library interposition?

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Overview of P6 Address Translation
CPU
32
L2 and DRAM
result
20
12
virtual address (VA)
VPN
VPO
L1 miss
L1 hit
4
16
TLBT
TLBI
L1 (128 sets, 4 lines/set)
TLB hit
TLB miss
...
...
TLB (16 sets, 4 entries/set)
10
10
VPN1
VPN2
20
12
20
5
7
PPN
PPO
CT
CO
CI
physical address (PA)
PDE
PTE
Page tables
PDBR
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Cache Structure

• 1-byte word
• 13-bit physical address
• 4-way associative cache, 4-byte block, 32 line