Texas Instruments inputs for Coverage Interoperability Forum

1
Texas Instruments inputs for Coverage
Interoperability Forum

• Design Verification Team

2
Texas Instruments DV metrics and closure

• TI uses many verification metric - each metric
  has a target at each design milestone. Sign-off
  is functional coverage based
• Detail coverage plan is written / reviewed in the
  beginning and updated during development

• Bugs (logic, DV)
• Source code activity ( lines / edits)
• IP releases to chip
• Cycles / bug for random testing
• Test development / regression
• Looking at
• Simulation farm efficiency metrics
• DV Resource metrics forecast vs ramp

• Functional coverage
• Level1 Features
• Level2 Cross
• Level3 Scenario
• Input/output/internal/corner case coverage
• Code coverage (line, branch, toggle, condition,
  expression, FSM)
• Formal verification (not used as sign-off) -e.g.
• assertions coded / passing
• Line coverage of logic cone
• Expression coverage of logic cone

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Design development
Test plan Coverage plan Test bench plan
Plan review Feedback, Refine plan
Define
Chip
Physical Design
RTL verification
Integration
Planning
gt80 done
Basic testing
Planning
100 verification
Reviews
IP
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How we use all metrics for closure

• TI has internal methodology/solution to view all
  metrics in a unified manner
• Based on mySQL database over a web browser.
• Allows all projects to track in a standard
  fashion.
• Solution is independent of EDA tools
• Right now supports coverage, test results,
  bugs, cycles
• Helps
• Grading of tests for coverage
• Measuring stimulus quality independent and/or in
  unison with correctness results
• Creates trend charts to show progression
• Combine different metrics to help trend analysis
  for closure

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Automated DV Dashboard
Formal Tools
Simulation Tools
Regression logs
Internal Tools
DV FLOW
Coverage logs
UPLOAD (Convert to common format)
Simulation Test Database
Coverage SQLDB
Regression SQLDB
Defects SQLDB
Coverage monitor Database
Bug Tracking
Formal Property Database
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Texas Instruments expectation out of CIF

• Common "definition" of coverage - between dynamic
  (simulation, emulation) and static (formal).
• ESL/Apps coverage
• Formal coverage / Assertion metrics
• Have we written enough properties?
• Have we over constrained the design?
• Define a standard format / method to create
  coverage - independent of verification language
  and technology (E/SV, PSL/SVA, SIM/FV).
• Unified common database/API which all tools can
  use for reading / writing. API needs to be open
  for users to write their own applications (like
  TI dashboard as we use today)
• Ability to merge all types of coverage data and
  derive relationship with other metrics
  (bugs/source code change and other metrics) for
  predictability analysis
• Call for action to all EDA vendors to support the
  format and interoperability

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CIF follow-up

• Influence standards bodies to include functional
  and formal coverage requirements into standard
  specs.
• Link functional spec and design spec to coverage
• Coverage planning
• How do we know whether we have defined good
  quality coverage?
• How do we define appropriate coverage for
  Simulation and formal during planning stage?
• How do we derive coverage directly from
  functional specification?
• Coverage collection
• How to define in a standard way
• When to collect (module vs system simulation vs
  formal)
• How to assign priority / importance