Pyxis

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Pyxis

• April Lewis
• Aaron Martin
• Steve Sherk

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Pyxis1600

• General-purpose 16-bit RISC microprocessor
• 16 16-bit registers
• 16-bit address bus
• Up to 64KB of addressable memory

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Registers

• 16 registers
• 3 special purpose
• r0 zero
• r14 stack pointer
• r15 return address
• 13 general purpose
• r1 - r13
• Status register (sr)
• 8 bits carry (c), overflow (o), negative (n),
  zero (z), interrupt enable (i), less than (l), 2
  bits unused
• Program counter (pc)
• Accumulator high (ah) and accumulator low (al)
• Used for multiply and divide
• Interrupt Return Address (IRA)
• Register to hold return address from interrupt

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Instruction Formats
0
3
15
4
7
8
9
R-type
opcode
rd
rs
ext
0
15
Displacement / Immediate
0
8
9
12
13
15
opcode
branch type
address
B-type

• 16-bit instructions
• 7-bit opcode
• 1 bit to indicate information in next word
• rd is source and target
• rs is source
• Branch instructions use special format

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Instruction Set
Category Instruction Example Opcode 159 Opcode8 Meaning
Arithmetic add add ltrdgt,ltrsgt 0000001 0 r3 r3 r4
Arithmetic add immediate addi ltrdgt, 100 0000001 1 r3 r3 100
Arithmetic subtract sub ltrdgt, ltrsgt 0000010 0 r3 r3 - r4
Arithmetic subtract immediate subi ltrdgt, 200 0000010 1 r3 r3 - 200
Arithmetic divide div ltrdgt, ltrsgt 0000100 0 ltah, algt r3 / r4
Arithmetic divide immediate divi ltrdgt, 4 0000100 1 ltah, algt r3 / 4
Arithmetic multiply mult ltrdgt, ltrsgt 0000011 0 ltah, algt r3 r4
Arithmetic multiply immediate multi ltrdgt, 6 0000011 1 ltah, algt r3 6
Arithmetic move from al mal ltrdgt 1010000 x r4 (al)
Arithmetic move from ah mah ltrdgt 1011111 x r4 (ah)
Data Transfers load word lw ltrdgt, 100(ltrsgt) 0011111 1 r3 Memoryr4 100
Data Transfers store word sw 200(ltrdgt), ltrsgt 0010000 1 Memoryr3 200 r4
Logical and and ltrdgt, ltrsgt 0000100 0 r3 r3 r4
Logical andi andi ltrdgt, 4 0000100 1 r3 r3 4
Logical or or ltrdgt, ltrsgt 0000101 0 r3 r3 r4
Logical ori ori ltrdgt, 4 0000101 1 r3 r3 4
Logical nor nor ltrdgt, ltrsgt 0000110 0 r3 (r3 r4)
Logical nori nori ltrdgt, 4 0000110 1 r3 (r3 4)
Logical comp comp ltrdgt, ltrsgt 1111111 0 set sr bits after compare
Logical shl shl ltrdgt, 10 0000111 0 r3 r3 ltlt 10
Logical shr shr ltrdgt, 10 0001000 0 r3 r3 gtgt 10
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Instruction Set
Category Instruction Example Opcode 159 Opcode8 Meaning
Conditional Branch beq beq 100 1110000 x if srz 1, go to PC 100
Conditional Branch bne bne 100 1110001 x if srz 0, go to PC 100
Conditional Branch blt blt 100 1110010 x if srl 1, go to PC 100
Conditional Branch bgt bgt 100 1110011 x if (srl 0) (srz 0), go to PC 100
Unconditional Branch jmp jmp 2500 100xxxx 1 go to 2500
Unconditional Branch jmpl jmpl 2500 011xxxx x r15 PC 2, go to 2500
Unconditional Branch jmpr jmpr ltrdgt 010xxxx x go to r4
Other reti reti 001001 x enables interrupts and reloads PC
Other no operation nop 0000000 x stall for one clock cycle
Assembly to Machine Code Example
add r3, r4 comp r10, r4 beq 25 jmpr r9
0000001 0 0011 0100 1111111 1 1010 0100 1110000 x
xxxx xxxx 0000 0000 0001 1001 010xxxx x 1001 0000
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Addressing Modes

• Register direct
• Register indirect plus displacement
• Use r0 for absolute addressing
• PC-relative
• Immediate

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Datapath
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Control Signals
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Control Signals
Actions of n-bit Control Signals Actions of n-bit Control Signals Actions of n-bit Control Signals
Signal Name Effect When Deasserted Effect When Asserted
ALUSrcA 00 The first input to the ALU is the contents of the A register
  01 The first input to the ALU is the contents of the Memory Data Register
  10 The first input to the ALU is the value of the PC
  11 None
ALUSrcB 00 The second input to the ALU is the contents of the B register
  01 The second input to the ALU is the contents of the Memory Data Register
  10 The second input to the ALU is the value 2
  11 The second input to the ALU is the value of the Instruction Register 80
ALUOp 000 Add
  001 Subtract
  010 AND
  011 OR
  100 NOR
  101 Set on less than
  110 Multiply
  111 Divide
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State Transition Diagram
0
Fetch
1
IorD0 MemRead1 MemWrite0 ALUOpADD ALUSrcA2 AL
USrcB2 PCSrc0 PCWrite1 RegWrite0
Decode
R-type (ext1)
Fetch Immediate
4
R-type (ext0)
2
Execute
Calc EA
Calc EA or Immediate
8
Write-back ALU to Reg
3
5
Memory Write
Memory Read
9
6
To State 0
Write-back Mem to Reg
15
7
Check Interrupt
12
State Transition Diagram
Fetch
Decode
0
1
R-type Jump Link
R-type Jump (ext1)
R-type Jump (ext0)
B-type
Save Return Addr
13
Jump to Reg Addr
Compare
10
12
14
Jump
11
Update PC
To State 15
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Interrupts

• Interrupts will be checked at the completion of
  each instruction
• An interrupt will trigger some extra states that
  send the processor to an Interrupt Service
  Routine (ISR), pre-programmed in code memory.
• These states will perform the following
• Save the processors state
• Disable interrupts
• Jump to the ISR
• The RETI instruction will return the processor
  from the ISR

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Virtex XCV300 FPGA

• XCV300 FPGA
• - 322,970 logic gates
• - 8 KB on-chip RAM
• - Block SelectRAM
• - Fast arithmetic carry
• - Clock Speed 10MHZ
• - Multiple I/O standards (LVTTL, LVCOMS2)

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Input / Output Serial Interface

• UART Transmitter and Receiver Macros

UART_TX
UART_RX
8-bit
Serial
Serial
16 Byte FIFO BUFFER
8-bit
16 Byte FIFO BUFFER
These macros are fully compatible with standard
UART communications protocols such as to a PC,
providing level shifting components are employed
to generate RS232 signaling. The buffers will be
interrupt driven.
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Memory Timing Diagrams

• 32KB FLASH (AT29C256-70PC)

Total access time is 70ns (tACC)
70ns
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Memory Timing Diagrams

• 32KB SRAM (K6x0808C1D-DF70)

Total access time is 70ns (tAA)
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32KBx8 off-chip SRAM32KBx8 off-chip FLASH
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Parts List
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Roles and Responsibilities

• Aaron
• Logic design
• Verilog programming
• Hardware implementation
• April
• Logic design
• Verilog programming
• Assembler
• Steve
• Logic design
• Verilog programming
• Hardware implementation
• All
• Test programs
• Integration and Test
• Documentation

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Schedule
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Questions