Pyxis

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Pyxis

• Aaron Martin
• April Lewis
• Steve Sherk

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Pyxis1600

• General-purpose 16-bit RISC microprocessor
• 16 16-bit registers
• 24-bit address bus
• Up to 16MB of addressable memory

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Registers

• 16 registers
• 3 special purpose
• r0 zero
• r14 stack pointer
• r15 return address
• 13 general purpose
• r1 - r13
• Status register (sr)
• 8 bits carry (c), overflow (o), negative (n),
  zero (z), interrupt enable (i), less than (l), 2
  bits unused
• Program counter (pc)
• Accumulator high (ah) and accumulator low (al)
• Used for multiply and divide
• Page register (pr)
• Sets the high order 8 bits in the 24-bit address
  space

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Instruction Formats
0
3
15
4
7
8
9
R-type
opcode
rd
rs
ext
0
15
Displacement / Immediate
0
8
9
12
13
15
opcode
branch type
address
B-type

• 16-bit instructions
• 7-bit opcode
• 1 bit to indicate information in next word
• rd is source and target
• rs is source
• Branch instructions use special format

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Instruction Set
6
Instruction Set
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Addressing Modes

• Register direct
• Register indirect plus displacement
• Use r0 for absolute addressing
• PC-relative
• Immediate

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Interrupts

• Options for handling interrupts
• Handled by hardware
• Each interface wired to its own pin
• Handled by software
• Use interrupt vector that points to different
  routines
• Have separate priority level for each interface
• All interrupts go to same routine that polls each
  device to see which one caused the interrupt

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Block Diagram Major Components
Instruction 158
Read / Write Register
Instruction 74
Instruction 30
Read Register
Memory
Registers
Instruction Register
15
8
7
4
3
0
OpCode Dest. Reg Source Reg
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Sub-systems

• Internal to the microprocessor
• Fetch and Memory access logic
• addressing modes
• ALU
• add, sub, mult, div, memory access calculations
  (PCoffset)
• Control logic
• micro instructions, control signal labels
• Register implementation
• External
• Serial bus implementation
• hardware associated with serial port

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Assembler

• Converts assembly code into machine language
• Uses a look-up table to find machine code for
  each instruction
• Some instruction are psudo-instructions
  implemented with other, lower level instructions
• Written in Perl and implemented on a PC
• Perl is good for parsing and string manipulation
• Machine code saved on EPROM and loaded onto
  microprocessor
• .asm ? .HEX ? EPROM burning software

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Hardware

• XCV300 FPGA
• - 322,970 logic gates
• - 8 KB on-chip RAM
• 128KB off-chip SRAM
• 128KB off- chip EPROM

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Input / Output Devices

• Serial RS232 port
• Monitor / LCD
• Keyboard / Keypad
• USB port

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Feature Priority

• General-purpose processor
• Multi-cycle design
• Complete reduced instruction set
• Some test code, Game, or Benchmark Program
• Assembler
• On-chip hardware divider
• C compiler
• Floating-point unit
• L1 data and instruction cache
• 5 stage pipeline design

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Roles and Responsibilities

• Aaron
• Logic design
• Verilog programming
• April
• Assembler
• Software interfaces
• Steve
• Hardware components
• Hardware interfaces
• All
• Integration and Test
• Documentation

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Schedule
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Risks and Contingency Plan
Risk Resolution
Problems in logic design Optional features will not be implemented
Bad Parts Several XCV300 chips are available, other components are inexpensive
Problems with hardware interfaces Several options exist (I.e. LCD vs. monitor, RS232 vs. USB)
Problems with software interfaces Validate all software interfaces early in schedule to allow time to correct if necessary
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Questions