Problem

1
Problem

• How do we leverage increasing transistor counts
  to get more performance?
• Current trend create special purpose hardware
  that idles most of its lifetime
• Many common tasks can be sped up with special
  purpose hardware.

2
Proposed Solution

• Dynamically reconfigurable hardware - FPGAs
• Standard CPU handles most execution
• Common instruction blocks compiled to FPGA
  hardware
• Greatly leverages parallelism perfect for inner
  loops
• As transistor count goes up, FPGA size can scale.

3
Means of Evaluation

• Profile to locate parallelism and most common
  execution paths in sample programs (Amdahl's
  Law).
• Construct hardware structures and analyze
  performance characteristics on todays FPGA
  compared to a regular CPU.
• Estimate FPGA startup time
• Calculate speedup for a given architecture and
  programming model

4
Related Works

• Much research into locating parallelism (ie
  VLIW, super computer)
• Our attempts at exploiting inner loop
  parallelism are in some ways similar to vector
  processors.
• GARP of Berkeley A True Implementation
  Compilation techniques
• Cell architectures

5
Desired Results

• FPGA startup time can be offset by speedup for an
  architecture and programming model of manageable
  complexity
• Many commonly used programs will benefit
• Speedup justifies chip space in light of
  alternative uses (ie more cache, more CPUs)
• Cost of production estimates are no greater than
  devices already providing similar performance