Title: Image compression based on energy clustering and zero-quadtree representation
1 POWER OPTIMIZED LCVCO MIXER
CO-DESIGN Daniel Götz, Milosz Sroka June
20th, 2006
MSICT RF Communication SoC
2PAPERS IMPLEMENTATION
OUR IMPLEMENTATION
RESULTS
CONCLUSION
INTRODUCTION
- Power Optimized LC VCO Mixer Co-design
- by Byunghoo Jung, Shubha Bommalingaiahnapallya,
and Ramesh Harjani University of Minnesota, Dept.
of ECE - Capacitively source degenerated buffer used as
a negative resistance cell - No need of cross-coupled scheme
- Reduced power consumption
- Mixer input capacitance incorporated into the
degeneration capacitor
3INTRO
OUR IMPLEMENTATION
RESULTS
CONCLUSION
PAPERS IMPLEMENTATION
- General implementation steps (1)
- LC Tank-based VCO Design
Parallel LC oscillator model
Requirements of negative resistance
Parallel LC oscillator model
Requirements of negative resistance
Buffer sizing and parameters calculation
Buffer sizing and parameters calculation
Tank design for oscillation frequency
Design of the VCO complete structure
Tank design for oscillation frequency
4INTRO
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CONCLUSION
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- General implementation steps (2)
- Mixer Design
- ? Standard Gilbert cell design
- ? Reduced noise figure, maximized conversion
gain - ? Input impedance characteristics
- VCO-Mixer Co-Design
- ? Incorporation of the mixer input impedance to
the VCO structure. - ? Other linkage effects
5INTRO
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- Step 1/6 Tank design
- Estimation of the oscillation frequency ? L, C
- ?
- Calculation of the parasitic resistance of L
- ? Graphically
- ? Approximation
- Required negative resistancefor compensation ?
Req
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- Step 2/6 Degenerated Negative Resistance Cell
- Dimensioning of the degenerating cell ? Cs,
width, Ibias, VDD
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- Step 3/6 Tank Re-design
- Calculation of the Ceq of the cell
- Re-design
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- Step 4/6 Oscillation structure
- Tank biasing
- Pulse generation
9INTRO
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OUR IMPLEMENTATION
- Step 5/6 Mixer design
- Standard Gilbert cell
- ? Transistor dimensioning
- ? R load
- ? I bias
- Input impedance
- ? R in series with C
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Step 5/6 Mixer design
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- Step 6/6 Co-design
- Linkage
- ? Mixer input impedance
- ? Tank tuning (not necessary)
- ? Linkage capacitance to eliminate DC offset
12INTRO
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CONCLUSION
OUR IMPLEMENTATION
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14INTRO
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VCO Transient analysis Single
ended Differential output
15INTRO
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RESULTS
PSS and Pnoise analysis
16INTRO
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CONCLUSION
- Comparison between paper and our implementation
- Low power design could not be achieved because
of, - Different Technology (paper 0.18µm, used
0.35µm) - Not sufficient good inductors (Q, parasitic
resistance) - comparable PSS results
- Phase noise was realized not that good as in the
paper. At 1GHz paper -107dBc/Hz our
implementation -52dBc/Hz - Discovered Bottleneck of this design
- Inductors because provide mainly the parasitic
resistance which should be compensated with the
Buffer-Transistors.