Direct Memory Access and DMAControlled IO

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Chapter 13

• Direct Memory Access and DMA-Controlled I/O
• Barry B. Brey
• bbrey_at_ee.net

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DMA

• Direct Memory Access (DMA) is a method whereby
  the memory and I/O space of the microprocessor
  can be accessed directly without the intervention
  of the microprocessor or a program.
• During a DMA access the microprocessor is turned
  off by placing a logic one on the HOLD input.
• After placing a logic one on HOLD, the
  microprocessor issues a logic one on the HLDA to
  indicate a hold is in effect.

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• During a HOLD, the microprocessor stops running
  the program and it places its address, data, and
  control bus connections at their impedance state.
  This in effect is the same as removing the
  microprocessor from its socket!
• While the microprocessor is held, other devices
  are free to gain access to its memory and I/O
  space to directly transfer data.

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• HOLD has a higher priority than interrupts and
  HOLD takes effect in a clock or two.
• The only input with a higher priority than HOLD
  is the RESET input to the microprocessor.

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DMA Control Signals

• On early Intel microprocessor the control signals
  were not DMA compatible without additional
  circuitry.
• Because during a DMA, the memory and I/O are
  accessed simultaneously, 4 control signals are
  needed. The next slide illustrates a multiplexer
  used to generate these signals.

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8237 DMA Controller

• The chipset in a modern computer contains a pair
  of 8237 DMA controllers to provide 8 DMA
  channels.
• The only feature not supported by the chipset is
  the memory-to-memory DMA transfer described for
  the 8237 DMA controller integrated circuit.
  Intel removed this feature from the chipset
  because of the system architecture.

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DMA Command Register
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DMA Mode Register
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DMA Request Register
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Mask Set/Reset Register
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DMA Mask Register
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Status Register
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8237 Port Assignments
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8237 Channel Registers
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DMA Page Registers
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A procedure that transfers a block of data using
the 8237A DMA controller in Figure 13-12. This
is a memory-to-memory transfer. Calling
parameters SI source address DI
destination address CX count ES segment
of source and destination LATCHB EQU 10H CLEARF EQ
U 7CH CHOA EQU 70H CH1A EQU 72H CH1C EQU 73H MO
DE EQU 7BH CMMD EQU 78H MASKS EQU 7FH REQ EQU 7
9H STATUS EQU 78H TRANS PROC NEAR USES AX MOV
AX,ES program latch B MOV AL,AH SHR
AL,4 OUT LATCHB,AL OUT CLEARF,AL clear F/L
MOV AX,ES program source address SHL
AX,4 ADD AX,SI OUT CH0A,AL MOV AL,AH OUT
CH0A MOV AX,ES program destination
address SHL AX,4 ADD AX,DI OUT CH1A,AL MOV
AL,AH OUT CH1A,AL
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MOV AX,CX program count DEC AX OUT
CH1C,AL MOV AL,AH OUT CH1C,AL MOV
AL,88H program mode OUT MODE,AL MOV
AL,85H OUT MODE,AL MOV AL,1 enable block
transfer OUT CMMD,AL MOV AL,0EH unmask
channel 0 OUT MASKS,AL MOV AL,4 start
DMA OUT REQ,AL .REPEAT wait for
completion IN AL,STATUS .UNTIL AL
1 RET TRANS ENDP
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A procedure that clears the DOS mode video
screen. using the DMA controller as depicted
in Figure 13-12. Calling sequence DI
offset address of area cleared ES segment
address of area cleared CX number of bytes
cleared LATCHB EQU 10H CLEARF EQU 7CH CHOA EQU 70
H CH1A EQU 72H CH1C EQU 73H MODE EQU 7BH CMMD
EQU 78H MASKS EQU 7FH REQ EQU 79H STATUS EQU 78H
ZERO EQU 0 CLEAR PROC NEAR USES AX MOV
AX,ES program latch B MOV AL,AH SHR
AL,4 OUT LATCHB,AL OUT CLEARF,AL clear F/L
MOV AL,ZERO save zero in first byte MOV
ESDI,AL MOV AX,ES program source
address SHL AX,4 ADD AX,SI OUT CH0A,AL MOV
AL,AH OUT CH0A
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MOV AX,ES program destination address SHL
AX,4 ADD AX,DI OUT CH1A,AL MOV AL,AH OUT
CH1A,AL MOV AX,CX program count DEC AX OUT
CH1C,AL MOV AL,AH OUT CH1C,AL MOV
AL,88H program mode OUT MODE,AL MOV
AL,85H OUT MODE,AL MOV AL,03H enable block
hold transfer OUT CMMD,AL MOV AL,0EH enable
channel 0 OUT MASKS,AL MOV AL,4 start
DMA OUT REQ,AL .REPEAT IN
AL,STATUS .UNTIL AL 1 RET CLEAR ENDP
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A procedure that prints data via the printer
interface in Figure 13-13 Calling
sequence BX offset address of printer
data DS segment address of printer data CX
number of bytes to print LATCHB EQU 10H CLEARF E
QU 7CH CH3A EQU 76H CH1C EQU 77H MODE EQU 7BH C
MMD EQU 78H MASKS EQU 7FH REQ EQU 79H PRINT PROC
NEAR USES AX CX BX MOV EAX,0 MOV
AX,DS program latch B SHR EAX,4 PUSH AX SHR
EAX,16 OUT LATCHB,AL POP AX program
address OUT CH3A,AL MOV AL,AH OUT
CH3A,AL MOV AX,CX program count DEC AX OUT
CH3C,AL MOV AL,AH OUT CH3C,AL MOV
AL,0BH program mode OUT MODE,AL MOV
AL,00H enable block mode transfer OUT
CMMD,AL MOV AL,7 enable channel 3 OUT
MASKS,AL RET PRINT ENDP
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A procedure that tests for completion of the DMA
action STATUS EQU 78H TESTP PROC NEAR USES
AX .REPEAT IN AL,STATUS
.UNTIL AL 8 RET TESTP ENDP
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