superscalars

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superscalars

• Lalitha Ramadoss
• Elec 6200 Computer Architetcure Design
• Lectured by Dr.Vishwani Agrawal
• Electricalcomputer Engineering
• Auburn

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What is a superscalar processor?

• Execute more than one instruction in each cycle
• Exploits Instruction level parallelism
• Motivation is PipeliningParallelism
• Better performance
• IBM RS/6000, TI SuperSPARC, the HP PA7100, and
  the DEC AXP 21064

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Simple superscalar

INT
IF
ID
MEM
WB
FP
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Advanced Superscalars
WB
INT
MEM
IF
ID
FP
WB
MEM
IF
ID
IF
ID
Lw/sw
MEM
WB
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Instruction Level Parallelism

• Increasing the depth of pipeline to overlap more
  instructions-number of stages increased
• Replicating the internal components-multiple
  issue technique

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Superscalar History

• Cray CDC 6600-1965
• Intel i960CA-1988,AMD-29000(1990)-RISC
• P6 PentiumPro and PentiumII,Intel80386-CISC
• Power PC970

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Superscalar concepts

• Scheduling
• Issues
• Execution
• Speculation
• WriteBack
• Retirement or Completion

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Superscalar Classification

• Static Superscalars-execute instructions in
  program order
• Dynamic Superscalars-execute instructions out of
  order
• Dynamic with Speculation-ability to speculate on
  branches

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Data Dependencies and Hazards

• Output Dependency
• MUL R1, R4, 15 R1 R4 15
• ADD R2, R1, 1 R2 R1 1
• MOVE R1, R3 R1 R3
• Antidependency
• ADD R1, R2, 1 R1 R2 1
• MOVE R2, R3 R2 R3

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Dynamic multiple issue processors

• Scheduling by Hardware
• lw t0,20(s2)
• add tl,t0,t2
• sub s4,s4,t3
• Dynamic Pipeline scheduling

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Dynamic scheduled Processors
IFID
RS
RS
RS
RS
FP
Int
Int
FP
Commit unit
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References

• Computer OrganizationDesign Patterson Hennessy-2
  3 edition
• http//www.cs.swan.ac.uk/csneal/HPM/superscalar.h
  tml
• http//en.wikipedia.org/wiki/Superscalar
• http//www.ipp.mpg.de/de/for/bereiche/stellarator/
  Comp_sci/CompScience/csep/csep1.phy.ornl.gov/ca/no
  de25.html

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