Learning Outcomes

1
(No Transcript)
2
Learning Outcomes

• At the end of this chapter, the students should
  be able to
• Analyzed or design of a transistor amplifier
  that require a dc response of the system
• Understand dc level of operation points of a
  transistor
• Understand the possible operating points of a
  transistor
• Derived an equation of network configurations

3

• INTRODUCTION
• BJTs amplifier requires a knowledge of both the
  DC analysis (LARGE - signal) and AC analysis
  (small - signal).
• Once the desired DC current and voltage levels
  have been
• defined, a network must be constructed that will
  establish the
• desired operating point.
• BJT need to be operate in active region used as
  amplifier.
• The cutoff and saturation region used as a
  switches.
• The following basic relationship for a
  transistor are requires for analysis of network
  configuration

4

• INTRODUCTION(CONTINUED)
• DC bias analysis ? assume all capacitors are
  open cct.
• AC bias analysis
• 1) Kill all DC sources
• 2) Assume coupling capacitors are short cct. The
  effect of there capacitors is to set a lower
  cut-off frequency for the cct.
• 3) Inspect the cct (replace BJTs with its small
  signal model).
• 4) Solve for voltage and current transfer
  function and i/o and o/p impedances.
• Transistor amplifiers
• ? resulting DC current and voltage establish an
  operating point
• ? region that can be employed for amplification
  process.
• BJT to be biased in active operating region the
  following must be true
• 1) BE junction forward biased
• 2) BC junction reverse biased

5
Various operating points within the limits of
operation of a transistor
6
TRANSISTOR BIASING CCT
DC ANALYSIS
AC ANALYSIS
FIXED-BIAS CCT
7

• Forward Bias of Base-Emitter
• This cct also known as input loop.

8

• Collector-Emitter Loop
• Also known as output loop.

The value of IC, IB and VCE shows the position of
Q-point at o/p graph. The notation of this value
changes to ICQ, IBQ and VCEQ.
9
Example 1 Determine the following cct for the
fixed bias configuration a) IBQ and ICQ b)
VCEQ c) VB and VC d) VBC
10
Example 2 Determine the following for the fixed
bias configuration a) IBQ and ICQ b) VCEQ c) VB
d)VC e) VE
11
Example 3 Determine the following for the fixed
bias configuration a) IC b) RC c)RB d)VCE
IC
RB
RC
VC 6 V ? 80
VCE
IB 40 ?A
12

• Transistor Saturation
• Saturation means the level of systems have
  reached their maximum values.
• For a transistor operating in the saturation
  region, the current is maximum value for a
  particular design.
• Saturation region are normally avoided because
  the B-C junction is no longer reverse-biased and
  the o/p amplified signal will be distorted.

12
13
The saturation current for the fixed bias
configuration is

• Fig above shows the schematic diagram to
  determine
• ICsat for the fixed-bias configuration.

14
Example 4 By refering to example 1 determine the
saturation level. Solution
Icsat Vcc/Rc 12/2.2k 5.45 mA The design of
example 1 in ICQ 2. 34 mA. It can be
concluded theICQ is operated within the limit
15
Example 5 Find the saturation current for the
fixed-bias configuration example 2 Solution
Icsat Vcc/Rc 16/2.7k 5.92 mA The design of
example 1 in ICQ 2. 93 mA. It can be
concluded theICQ is operated within the limit
16

• Load line analysis
• - By refering to fig on output loop one straight
  line can be draw at output characteristics. This
  line is called load line.
• - This line connecting each separate of Q-point.
• - At any point along the load line, values of IB,
  IC and VCE can be picked off the graph.
• The process to plot the load line as follows
• Step 1
• Refer to fig. on o/p loop, VCEVCC ICRC (1)
• Choose IC0 mA. Subtitute into (1), we get
• VCEVCC (2) ?? located at X axis

16
17
Step 2 Choose VCE0V and subtitute into (1), we
get ICVCC/RC (3) ?? located at Y-axis Step
3 Joining two points defined by (2) (3), we
get straight line that can be drawn as below
17
18

• Case 1
• Level IB changed by varying the value of RB.
• Q-point moves up and down

19

• Case 2
• VCC fixed and RC change the load line will shift
  as shown
• IB fixed, the Q-point will move as shown in the
  same figure.

20

• Case 3
• RC fixed and VCC varied, the load line shifts as
  shown

20
21
Example 6 Given the load line below and defined
Q-point, determine the required values of VCE, RC
and RB for a fixed bias configuration.
22
Example 7 Determine the value of Q-point for
Fig. below . Also find the new value of Q-point
if ? change to 150.
22
23
Solution
24

• EMITTER-STABILIZED BIAS CCT
• The DC bias network of below contains an emitter
  resistor to improve the stability level of
  fixed-bias configuration.
• The analysis consists of two scope
• ??Examining the base-emitter loop (i/p loop)
• ??Use the result to investigate the
  collector-emitter loop (o/p loop)

25
Base-Emitter Loop (i/p loop)
26
Collector-Emitter Loop (o/p loop)
26
27
Example 8 For the emitter-bias network for Fig.
below determine a)IB b)IC c)VCE
d)VC e)VE f)VB g)VBC
27
28
Improved Bias Stability Issues Comparison
analysis for example 1 and example 8.
Data from example 8 (emitter-bias configuration)
28
29
Takehome exercise For the emitter-stabilized
biase cct below, determine IBQ, ICQ, VCEQ, VC,
VB, VE.
30
The saturation current for an emitter-bias
configuration is
31
Example 9 Determine the saturation current for
the network of example 8. Solution This
value is about three times the level of ICQ
(2.01mA? ?50) for the example 8. Its indicate
the parameter that been used in example 8 can be
use in analysis of emitter bias network.
32

• Load line analysis
• The process to plot the load line as follows
• Step 1
• Refer to fig. VCE VCC IC(RCRE) (1)
• Choose IC 0 mA. Subtitute into (1), we get
• VCEVCC (2) ? located at X axis
• Step 2
• Choose VCE 0V, subtitute into (1) gives

33
Step 3 Joining two points defined by (2)
(3), we get straight line that can be drawn as
below
34
VOLTAGE-DIVIDER BIAS

• ICQ and VCEQ from the table of example 8 is
  changing
• dependently the changing of ?.
• The voltage-divider bias configuration such as in
  next Fig. is designed to have a less dependent or
  independent of ?.
• If the cct parameter are properly choosen, the
  resulting
• levels of ICQ and VCEQ can be almost totally
  independent
• of ?.

35

• Two method for analyzed the voltage-divider bias
  configuration
• a) Exact analysis
• b) Approximate analysis

36

• Exact Analysis
• Step 1
• The i/p side of the network of previous Fig. can
  be
• redrawn as shown in below for DC analysis.
• Step 2
• Analysis of Thevenin equivalent network to the
  left of
• base terminal

37
Exact Analysis Step 2(a) Replaced the voltage
sources with short-cct equivalent as shown in
Fig. below and gives us the value of RTH
38
Exact Analysis Step 2(b) Determining the ETH by
replaced back the voltage sources and open cct
Thevenin voltage as shown in Fig. 5.21. Then
apply the voltage-divider rule.
39
Exact Analysis Step 3 The Thevenin network is
then redrawn as shown in Fig. below and IBQ can
be determined by KVL
39
40
Example 10Determine the DC bias voltage VCE and
current IC for the voltage-divider configuration
of network below
41
Solution
42
Example 11 For the voltage-divider bias
configuration of Fig. 5.23, determine IBQ, ICQ,
VCEQ, VC, VE and VB.
43
Approximate Analysis Step 1 ?RE ? 10R2 Step
2 The i/p section can be represented by the
network of Fig. below. R1 and R2 can be
considered in series by assuming I1?I2 and IB
0A .
44
Approximate Analysis Step 3
45
Example 12Repeat the analysis of example 10
using the approximate technique and compare
solution for ICQ and VCEQ. Solution
46
(No Transcript)
47
Example 13Repeat the exact analysis of example 9
if ? is reduced to 70. Compare the solution for
ICQ and VCEQ. Solution
47
48
Example 14Determine the levels of ICQ and VCEQ
for the voltage-divider configuration for below
using the exact and approximate analysis.
Compare the solution.
49
The saturation collector-emitter cct for the
voltage-divider configuration has the same
appearance as the emitter-biased configuration as
shown in Fig. below
50

• Load line analysis
• The similarities with the o/p cct of the
  emitter-biased configuration result in the same
  intersections for the load line of the
  voltage-divider configuration.
• The load line therefore have the same appearance
  with

51

• References
• Thomas L. Floyd, Electronic Devices, Sixth
  edition, Prentice Hall, 2002.
• Robert Boylestad, Electronic Devices and
  Circuit Theory, Eighth edition, Prentice Hall,
  2002.
• 3. Puspa Inayat Khalid, Rubita Sudirman, Siti
  Hawa Ruslan,
• ModulPengajaran Elektronik 1, UTM, 2002.
• 4. Website http//www2.eng.tu.ac.th