Multiplier: Functions

1
Multiplier Functions

• Discussion D7.2
• Example 19

2
Multiplier

• Binary Multiplication
• A VHDL Multiplier
• The Multiplication Operator
• A Multiplication Function

3
Binary Multiplication
4
Binary Multiplication
13 x 12 26 13 156
1101 1100 0000 0000 1101
1101 10011100
5
Hex Multiplication
6
Hex Multiplication
Dec
Hex
61 x 90 5490
3D x 5A 262 A x D 82, A x 3 1E 8
26 131 5 x D 41, 5 x 3 F 4 13
157216 549010
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Multiplication
1101 x1011 1101 1101 100111
0000 100111 1101 10001111
13 x11 13 13 143 8Fh
8
Multiplier

• Binary Multiplication
• A VHDL Multiplier
• The Multiplication Operator
• A Multiplication Function

9
1101 x1011 1101 1101 100111
0000 100111 1101 10001111
10
-- Example 19a 4-bit multiplier library
IEEE use IEEE.STD_LOGIC_1164.all use
IEEE.STD_LOGIC_unsigned.all entity mult4a is
port( a in STD_LOGIC_VECTOR(3 downto 0)
b in STD_LOGIC_VECTOR(3 downto 0) p out
STD_LOGIC_VECTOR(7 downto 0) ) end
mult4a architecture mult4a of mult4a
is begin process(a,b) variable pv,bp
STD_LOGIC_VECTOR(7 downto 0) begin pv
"00000000" bp "0000" b for i in 0 to 3
loop if a(i) '1' then pv pv
bp end if bp bp(6 downto 0)
'0' end loop p lt pv end process
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Multiplier Simulation
12
Multiplier

• Binary Multiplication
• A VHDL Multiplier
• The Multiplication Operator
• A Multiplication Function

13
-- Example 19a 4-bit multiplier library
IEEE use IEEE.STD_LOGIC_1164.all use
IEEE.STD_LOGIC_unsigned.all entity mult4b is
port( a in STD_LOGIC_VECTOR(3 downto 0)
b in STD_LOGIC_VECTOR(3 downto 0) p out
STD_LOGIC_VECTOR(7 downto 0) ) end
mult4b architecture mult4b of mult4b
is begin p lt a b end mult4b
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Multiplier

• Binary Multiplication
• A VHDL Multiplier
• The Multiplication Operator
• A Multiplication Function

15
-- Example 19c 4-bit multiplier function library
IEEE use IEEE.STD_LOGIC_1164.all use
IEEE.STD_LOGIC_unsigned.all entity mult4c is
port( sw in STD_LOGIC_VECTOR(7 downto 0)
ld out STD_LOGIC_VECTOR(7 downto 0)
) end mult4c
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architecture mult4c of mult4c is function
mul(a,b in STD_LOGIC_VECTOR)
return STD_LOGIC_VECTOR is variable pv,bp
STD_LOGIC_VECTOR(7 downto 0) begin pv
"00000000" bp "0000" b for i in 0 to 3
loop if a(i) '1' then pv pv bp end
if bp bp(6 downto 0) '0' end
loop return pv end function
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signal a1 STD_LOGIC_VECTOR(3 downto
0) begin a1 lt sw(7 downto 4) ld lt
mul(a1,sw(3 downto 0)) end mult4c
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Multiplier

• Binary Multiplication
• A VHDL Multiplier
• The Multiplication Operator (revisited)
• A Multiplication Function

19
std_logic_arith.vhd
library IEEEuse IEEE.std_logic_1164.all package
std_logic_arith is type UNSIGNED is array
(NATURAL range ltgt) of STD_LOGIC type SIGNED
is array (NATURAL range ltgt) of STD_LOGIC
subtype SMALL_INT is INTEGER range 0 to 1
function ""(L UNSIGNED R UNSIGNED) return
UNSIGNED function ""(L SIGNED R SIGNED)
return SIGNED function ""(L SIGNED R
UNSIGNED) return SIGNED function ""(L
UNSIGNED R SIGNED) return SIGNED function
""(L UNSIGNED R UNSIGNED) return
STD_LOGIC_VECTOR function ""(L SIGNED R
SIGNED) return STD_LOGIC_VECTOR function
""(L SIGNED R UNSIGNED) return
STD_LOGIC_VECTOR function ""(L UNSIGNED
R SIGNED) return STD_LOGIC_VECTOR
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function mult(A,B UNSIGNED) return UNSIGNED is
constant msb integerA'lengthB'length-1
variable BA UNSIGNED(msb downto 0)
variable PA UNSIGNED(msb downto 0)
begin if (A(A'left) 'X' or B(B'left)
'X') then PA (others gt 'X')
return(PA) end if PA
(others gt '0') BA
CONV_UNSIGNED(B,(A'lengthB'length))
for i in 0 to A'length-1 loop if A(i)
'1' then PA PABA
end if for j in msb downto 1 loop
BA(j)BA(j-1) end loop BA(0)
'0' end loop return(PA)
end
1101 x1011 1101 1101 100111
0000 100111 1101 10001111
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function ""(L UNSIGNED R UNSIGNED) return
UNSIGNED is begin return
mult(CONV_UNSIGNED(L, L'length),
CONV_UNSIGNED(R, R'length)) end
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std_logic_unsigned.vhd
library IEEE use IEEE.std_logic_1164.all use
IEEE.std_logic_arith.all
package STD_LOGIC_UNSIGNED is
function ""(L STD_LOGIC_VECTOR R
STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR
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std_logic_unsigned.vhd (cont.)
library IEEE use IEEE.std_logic_1164.all use
IEEE.std_logic_arith.all package body
STD_LOGIC_UNSIGNED is
function ""(L STD_LOGIC_VECTOR R
STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
constant length INTEGER
maximum(L'length, R'length)
variable result STD_LOGIC_VECTOR
((L'lengthR'length-1) downto 0) begin
result UNSIGNED(L) UNSIGNED(R)
return std_logic_vector(result) end