The 1st transistor ever built

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The 1st transistor ever built
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Transistor operation
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Chapter 4 DC biasing-BJTs
Faculty of Electrical and Electronic Engineering
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Topics objectives

• Youll learn
• Q-point of a transistor operation
• About DC analysis of a transistor circuit
• About Transistor biasing configuration
• Other available transistor biasing circuits
• Stability factor for transistor
• Transistor switching

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• INTRODUCTION
• BJTs amplifier requires a knowledge of both the
  DC analysis (LARGE-signal) and AC analysis (small
  signal).
• For a DC analysis a transistor is controlled by
  a number of factors including the range of
  possible operating points.
• Once the desired DC current and voltage levels
  have been
• defined, a network must be constructed that will
  establish the
• desired operating point.
• BJT need to be operate in active region used as
  amplifier.
• The cutoff and saturation region used as a
  switches.
• For the BJTs to be biased in its linear or
  active operating
• region the following must be true
• a) BE junction ? forward biased, 0.6 or 0.7V
• b) BC junction ? reverse biased

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• INTRODUCTION(CONTINUED)
• DC bias analysis ? assume all capacitors are
  open cct.
• AC bias analysis
• 1) Neglecting all of DC sources
• 2) Assume coupling capacitors are short cct. The
  effect of these capacitors is to set a lower
  cut-off frequency for the cct.
• 3) Inspect the cct (replace BJTs with its small
  signal model).
• 4) Solve for voltage and current transfer
  function and i/o and o/p impedances.
• For transistor amplifiers the resulting DC
  current and voltage establish an operating point
  that define the region that can be employed for
  amplification process.

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Various operating points within the limits of
operation of a transistor

• Q-point C
• Concern on
• nonlinearities due to IB
• curves is rapidly changes
• in this region.

• Q-point B
• The best operating point
• for linear gain and largest
• possible voltage and current
• It is a desired condition for
• a small signal analysis

• Q-point A
• I0A, V0V
• Not suitable for
• transistor to operate

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FIXED-BIAS CCT
AC ANALYSIS
DC ANALYSIS
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EMITTER-STABILIZED BIAS CCT
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Voltage divider bias
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• Forward Bias of Base-Emitter
• Refer to fig. 5.1. This cct also known as input
  loop.

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• Collector-Emitter Loop
• Refer to fig. 5.2. Also known as output loop.

The value of IC, IB and VCE shows the position of
Q-point at o/p graph. The notation of this value
changes to ICQ, IBQ and VCEQ.
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Example 1 Determine the following for the fixed
bias configuration of Fig 5.3. a) IBQ and ICQ b)
VCEQ c) VB and VC d) VBC
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Solution
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Example 2 Determine the following for the fixed
bias configuration of Fig 5.4. a) IBQ and ICQ b)
VCEQ c) VB d)VC e) VE
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Solution
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• Transistor Saturation
• Saturation means the level of systems have
  reached their maximum values.
• For a transistor operating in the saturation
  region, the current is maximum value for a
  particular design.
• Saturation region are normally avoided because
  the B-C junction is no longer reverse-biased and
  the o/p amplified signal will be distorted.
• Fig 5.5 shows the schematic diagram to determine
  ICsat for the fixed-bias configuration.

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The saturation current for the fixed bias
configuration is
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Example 3 By refering to example 1 and Fig. 5.3
determine the saturation level. Solution
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Example 4 Find the saturation current for the
fixed-bias configuration of Fig. 5.4. Solution
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• Load line analysis
• By refering to Fig. 5.2 (output loop) one
  straight line can be draw at output
  characteristics. This line is called load line.
• This line connecting each separate of Q-point.
• At any point along the load line, values of IB,
  IC and VCE can be picked off the graph.
• The process to plot the load line as follows
• Step 1
• Refer to fig. 5.2, VCEVCC ICRC (1)
• Choose IC0 mA. Subtitute into (1), we get
• VCEVCC (2) ? located at X axis

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Step 2 Choose VCE0V and subtitute into (1), we
get ICVCC/RC (3) ? located at Y-axis Step 3
Joining two points defined by (2) (3), we get
straight line that can be drawn as Fig. 5.6.
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• Case 1
• Level IB changed by varying the value of RB.
• Q-point moves up and down

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• Case 2
• VCC fixed and RC change the load line will shift
  as shown in Fig 5.8
• IB fixed, the Q-point will move as shown in the
  same figure.

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• Case 3
• RC fixed and VCC varied, the load line shifts as
  shown in Fig. 5.9

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Example 5 Given the load line of Fig. 5.10 and
defined Q-point, determine the required values of
VCE, RC and RB for a fixed bias configuration.
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Solution
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Example 6 Determine the value of Q-point for
Fig. 5.11. Also find the new value of Q-point if
? change to 150.
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Solution
The change of ?? cause the big change of Q-point
value. This shows that fixed biased configuration
is NOT stable
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• EMITTER-STABILIZED BIAS CCT
• The DC bias network of Fig 5.12 contains an
  emitter resistor to improve the stability level
  of fixed-bias configuration.
• The analysis consists of two scope
• Examining the base-emitter loop (i/p loop)
• Use the result to investigate the
  collector-emitter loop (o/p loop)

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• Base-Emitter Loop (i/p loop)
• Refer to fig. 5.12.

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• Collector-Emitter Loop (o/p loop)
• Refer to fig. 5.13.

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Example 7 For the emitter-bias network fo
Fig.5.14 determine a)IB b)IC c)VCE d)VC e)VE
f)VB g)VBC
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Solution
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Improved Bias Stability Issues Comparison
analysis for example 1 and example 7.
Data from example 1 (fixed-bias configuration)
Data from example 7 (emitter-bias configuration)
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Takehome exercise For the emitter-stabilized
biase cct of Fig. 5.15, determine IBQ, ICQ, VCEQ,
VC, VB, VE.
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Saturation
The saturation current for an emitter-bias
configuration is
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Example 8 Determine the saturation current for
the network of example 7. Solution ?
This value is about three times the level of ICQ
(2.01mA? ?50) for the example 7. Its indicate
the parameter that been used in example 7 can be
use in analysis of emitter bias network.
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• Load line analysis
• The process to plot the load line as follows
• Step 1
• Refer to fig. 5.13, VCEVCC IC(RCRE) (1)
• Choose IC0 mA. Subtitute into (1), we get
• VCEVCC (2) ? located at X axis
• Step 2
• Choose VCE0V, subtitute into (1) gives

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Step 3 Joining two points defined by (2)
(3), we get straight line that can be drawn as
Fig. 5.17
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VOLTAGE-DIVIDER BIAS
Data from example 7

• ICQ and VCEQ from the table of example 7 is
  changing
• dependently the changing of ?.
• The voltage-divider bias configuration such as in
  Fig.
• 5.18 is designed to have a less dependent or
  independent of
• the ?.
• If the cct parameter are properly choosen, the
  resulting
• levels of ICQ and VCEQ can be almost totally
  independent
• of ?.

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• Two method for analyzed the voltage-divider bias
  configuration
• Exact method
• Approximate method

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• Exact Analysis
• Step 1
• The i/p side of the network of Fig. 5.18 can be
• redrawn as shown in Fig. 5.19 for DC analysis.
• Step 2
• Analysis of Thevenin equivalent network to the
  left of
• base terminal

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Exact Analysis Step 2(a) Replaced the voltage
sources with short-cct equivalent as shown in
Fig 5.20 and gives us the value of RTH
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Exact Analysis Step 2(b) Determining the ETH by
replaced back the voltage sources and open cct
Thevenin voltage as shown in Fig. 5.21. Then
apply the voltage-divider rule.
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Exact Analysis Step 3 The Thevenin network is
then redrawn as shown in Fig. 5.22 and IBQ can be
determined by KVL
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Example 9Determine the DC bias voltage VCE and
current IC for the voltage-divider configuration
of network below
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Solution
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Example 10 For the voltage-divider bias
configuration of Fig. 5.23, determine IBQ, ICQ,
VCEQ, VC, VE and VB.
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Solution
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Approximate Analysis Step 1 ?RE ? 10R2 Step
2 The i/p section can be represented by the
network of Fig. 5.24. R1 and R2 can be considered
in series by assuming I1?I2 and IB 0A .
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Approximate Analysis Step 3
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NPN Transistor simulation
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Example 11Repeat the analysis of example 9 using
the approximate technique and compare solution
for ICQ and VCEQ. Solution
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ICQ and VCEQ are certainly close.
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Example 12Repeat the exact analysis of example 9
if ? is reduced to 70. Compare the solution for
ICQ and VCEQ. Solution
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Solution (continued)
Conclusion Even though ? is drastically half,
the level ICQ and VCEQ are essentially same.
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Example 13Determine the levels of ICQ and VCEQ
for the voltage-divider configuration fo Fig.
5.25 using the exact and approximate analysis.
Compare the solution.
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Solution
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Solution (continued)
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Solution (continued)
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The saturation collector-emitter cct for the
voltage-divider configuration has the same
appearance as the emitter-biased configuration as
shown in Fig. 5.27
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• Load line analysis
• The similarities with the o/p cct of the
  emitter-biased configuration result in the same
  intersections for the load line of the
  voltage-divider configuration.
• The load line therefore have the same appearance
  with

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DC Bias with Voltage Biasing
Another way to improve the stability of a bias
circuit is to add a feedback path from collector
to base. In this bias circuit the Q-point is only
slightly dependent on the transistor Beta ?.
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Base-Emitter Loop
Applying Kirchoffs voltage law VCC IC?RC
IBRB VBE IERE 0 Note IC? IC IB -- but
usually IB ltlt IC -- so IC? ? IC Knowing IC ?IB
and IE ? IC then VCC ?IB RC IBRB VBE
?IBRE 0 Simplifying and solving for IB

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Collector-Emitter Loop
Applying Kirchoffs voltage law IE VCE
IC?RC VCC 0 Since IC? ? IC and IC ?IB
IC(RC RE) VCE VCC 0 Solving for VCE

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Transistor Saturation Level
Load Line Analysis
It is the same analysis as for the voltage
divider bias and the emitter-biased circuits.
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Simulation of a NPN type common-emitter transistor
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Design Operation

• We are able to design the transistor circuit
  using the ideas that we have learnt before during
  analyzing dc biasing circuit.
• How?
• Understand the Kirchofs Law and other electric
  circuit law such as Ohms Law, Thevenin Laws etc
• Identify the parameters given
• Analyze into the input/output for the system and
  build a loop using electric circuits law.

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Miscellaneous configuration
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Examples
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Examples
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Examples of design

• Design of a bias circuit with an emitter feedback
  resistor
• Design of a current-gain-stabilized circuit (beta
  independent)

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Design of a bias circuit with an emitter feedback
resistor
The emitter resistor is ¼ to 1/10 of the supply
voltage
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Design of a current-gain-stabilized circuit (beta
independent)
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Transistor as switching networks

• Transistor works as an inverter in computer
  circuits.
• Operating point switch from cut-off to saturation
  along the load line for proper inversion.
• In order to understand, we assume that
• ICICEO0mA
• VCEVsat0V
• One must understand the transistor graph output
  and load-line analysis to describe and discuss
  about the transistor switching networks.

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Transistor as a switch
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Time interval
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Time interval continued
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Troubleshooting?

• How to define and encounter transistor circuit
  problem?

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PNP configuration
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Bias stabilization

• Stability of a system is a measure of the
  sensitivity of a network to variation in its
  parameter.
• ß increases with increase in temperature
• VBE decreases 7.5mV every degree celcius
• ICO doubles every 10 oC increase in temperature

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Effect of non-stability circuit/system
Room temperature
100oC temperature
Well find that ß increase after 100OC, base
current is same but not suitable to use due it is
very near to the saturation region.
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Stability factors
S(ICO)

• Emitter bias configuration

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S(ICO)

• Fixed bias configuration

• Voltage divider bias configuration

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S(ICO)

• Feedback bias configuration

• Physical impact

Fixed bias configuration ICßIB(ß1)ICO...IC
increase but IB maintain, so its not
stable Emitter bias configuration Increase IC
will increase ICO. It affect VE since
VEIEREICRE. In turn, the output loop will
inform that IB will decrease if VE is increase,
thus affect to reduce the collector
current. Feedback bias configuration same as
result of emitter bias configuration where IB
will decrease if IC increase. (IC proportional to
VRC) Voltage divider bias configuration Most
stable where as long as 10R2gtgt ßRE, VB remain
constant for any changing in IC.
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S(VBE)
S(ß)
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• References
• Thomas L. Floyd, Electronic Devices, Sixth
  edition, Prentice Hall, 2002.
• Robert Boylestad, Electronic Devices and
  Circuit Theory, Eighth edition, Prentice Hall,
  2002.
• 3. Puspa Inayat Khalid, Rubita Sudirman, Siti
  Hawa Ruslan,
• ModulPengajaran Elektronik 1, UTM, 2002.
• 4. Website http//www2.eng.tu.ac.th