Motivation

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Motivation
Need new methods of characterization, analysis,
design optimization for sampling /sensing
circuits!
High-Speed Digital Design Becoming Increasingly
Analog
Rail-to-Rail Assumption Challenged
or a Design Choice (e.g. Pipelined Comparators)
Partial Voltage Range a Design Reality (e.g.
Latches/FFs)
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Applications (among others)
High-Speed Interconnects
Ultra-Wideband Receiver Front End
Latches / Flip-Flops
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Sampling Function Aperture Time1
Characterization of sampling circuit as a linear
system via its impulse response. The Aperture
Time is a measure of the resolution of the
sampler.
Typical analysis and simulation plots of
differential transistor sampler for different
levels of approximation
Illustration of sampling function and aperture
time. In this case, Narrower is Better.
1 Johansson, H. O. and Svensson, C., Time
Resolution of NMOS Sampling Switches Used on
Low-Swing Signals, IEEE Journal of Solid-State
Circuits, vol. 33, pp. 237-45, February 1998.
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Differential Sampler Results
The following figures show the results for the
estimation of the Aperture Time using various
degrees of approximation. The analysis using
higher-order effects such as clock feedthrough
and input voltage swing has significantly better
results.
Problem with this approach Assumes linearity
not applicable in many circuits of interest. It
is important to investigate alternate methods of
analysis (Volterra series?) that apply to more
general sampling circuits.
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Characterization Methods - Sensing Function
Specify the output sample at the end of a clock
cycle as a function of the time difference
between input signal clock. This method is
generally applicable.
Example Sense Amplifier with ideal input
transmission gates and equilibrating
transistor1
In this case, Broader is Better!
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Input Stage Sizing for Latches/FFs
PowerPC Flip-Flop1
D-Latch Flip-Flop
The voltage in the internal nodes is determined
by the sampling operation of the driver stage and
is a function of sizing.
1Gerosa, G., A 2.2 W, 80 MHz Superscalar RISC
Microprocessor, IEEE Journal of Solid-State
Circuits, vol. 29, no. 12, Dec. 1994.
When the PMOS size of the inverter increases, it
takes less (more) time to establish a certain
voltage in the H-L (L-H) direction, i.e. Setup0 /
Hold0 (Setup1 / Hold 1) times decrease
(increase).
Circuit before clock switches
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Elmore Formula Analysis
Simple Master-Slave Flip-Flop with dynamic
latches for quantitative analysis

• Infinite setup-time case

• Individual stage delay

• Time constant at node SM (Elmores formula)

• Sampled value at node SM

• 5 Clk-Q delay degradation

Solving the above system of equations gives the
5 delay degradation setup/hold times.Using these
estimates, the optimal sizing for the driver
stage can be determined.
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Elmore Formula Analysis
The setup and hold curves for the two transitions
(0?1 and 1?0) are shown below for one of the
circuits examined. The blue (red) curves
represent the simulation (analysis) results. The
intersection points of the curves specify the
optimal PMOS sizing for the driver stage.
Hold Curves
Setup Curves
Agreement is not exact due to the inaccuracies in
the device modeling. More sophistication and
better calibration of the models will lead to
better results.
Advantages Gives some intuition, relatively
limited modeling (only transistors).
Disadvantages May produce large errors (due to
exponential representation).
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Physical Limits of Front-End Sampling1

• Limitations of interleaved sampling Front-End
• Clock jitter/skew
• Matching between individual switches (e.g. due
  to random dopant fluctuations)
• Low-Pass input filtering

H. O. Johansson, M. Horowitz, Sampling-Rate
Optimization of an Interleaved-Sampling
Front-End, IEEE ISCAS 2001, p. 573-6.

• Trade-offs in design
• Larger transistors have a narrower Sampling
  Function, but increase the input capacitance
• Larger number of switches provides larger
  sampling rate, but increases sensitivity of
  system to jitter/skew and matching issues, and
  also increases input capacitance
• Question What design choices give the highest
  sampling rate for acceptable voltage swing at the
  output?