Energy Modeling of the Cache Subsystem

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Energy Modeling of the Cache Subsystem

• Ankit Raizada (2006MCS2265)
• Under Guidance of
• Prof. Preeti Ranjan Panda

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Introduction

• Cache are significant part of processor based
  systems
• In terms performance
• In terms area
• In terms of energy dissipation
• Tools are available for Design space exploration
  (CACTI, ZOOM)
• Number of inaccuracies reported in energy
  estimation in this process 12 .

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Problem Statement

• To build a model which takes different cache
  parameters, trace of program execution
  corresponding to different types of access during
  program execution and implementation technology
  as input and produces an energy estimates for the
  cache due to sequence of transactions.
• Inputs
• Phase I Size, Line size, Associativity,
  Replacement Policy.
• Phase II Sub-line Size, Write Mode, Bus width,
  Prefetch size
• Phase III Transaction modeling
• Read, Write, Miss, Pre fetch, Flush, Invalidate.

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CACTI Brief Description

• Cache design exploration tool
• Finds the most optimal SRAM organization
• Estimates Area, Timing and Power of the cache

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Problems

• No consideration for the policy part of the
  controller
• Replacement Policy
• Write back
• No consideration to functional aspect of cache
• Energy dissipation in Hit type access and miss
  type access isnt same
• No option for the Low energy design architectural
  techniques in exploration
• Way prediction 4
• Way halting 4
• Objective function for the optimization of the
  cache design is inflexible
• Score W1Area W2Latency W3Energy

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Throat Clearing

• These problems do not mean that CACTI tool is
  useless
• CACTI is a design exploration tool so Fidelity of
  results is more important than Accuracy of
  estimations
• CACTI finds optimal SRAM organization
• This work (currently) is focused on improving the
  accuracy of estimates

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Replacement Policy

• Replacement policy logic is a significant portion
  of Cache Controller logic
• LRU is pretty widely used policy
• LRU updates its state history each time an access
  is made.
• Currently completely ignored by the CACTI (as of
  version 4.2)
• Need for an experimental model of LRU to estimate
  power from.

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LRU Model

• LRU using a simple systolic Array, an
  implementation level model
• Proposed by J.P. Grossman in A Systolic Array
  for Implementing LRU Replacement
• Essentially it implements a move-to-back list.

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LRU Systolic Array
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4
1
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0
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LRU
MRU
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1
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Systolic Array
Compare
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0
1
Latch
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Systolic Array
Compare
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2
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Latch
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Systolic Array
Compare
1
2
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0
3
Latch
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Systolic Array
Compare
1
2
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0
3
Latch
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Systolic Array
Compare
2
0
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3
Latch
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Array Node
L
?
Cur- rent Index
MUX
M
OR
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Implementation and Power Evaluation

• This LRU scheme was implemented in VHDL RTL
• Advantages
• For power Estimation
• Synthesized using Synopsis Design Compiler
• Europractice cell library for 180 nm process was
  used
• Static Time simulation was done to obtain traces

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Contd

• Finally Prime Power was used to evaluate the
  power (as a result of simulation)
• Per operation energy can then be easily found
• E (Avg Power) (Simulation Time) / (Number of
  state updates of LRU)
• This is what CACTI is discounting

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Result

• For a 32K 64 byte cache line 4-way cache on 180nm
  Technology (estimates by CACTI)
• Least Cycle Time possible 1ns
• Energy per Read 0.51 nJ
• Energy per Write 0.05 nJ

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Result

• For a 2-bit LRU (4 way associative cache)
• Clock cycle 1.0 ns (Constrain)
• Avg Power 3.89 mW
• Energy for 28 updates of LRU 0.56016 nJ
• Energy per 1 update 0. 02 nJ

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Analysis

• Assuming that Read and Write a equally probable
• Energy per cache access (0.51 0.05)/2 0.28
  nJ
• Approximately 6.6 percent of power of the cache
  access
• By Way Halting ,Way Prediction energy which is
  spent in the SRAM part of cache will go down
  (roughly by the order of the number of ways).

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Conclusion

• Discounting the LRU energy is NOT advisable
  especially in a low power cache while estimating
  power

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Timeframe Minor Project

• Literature survey ( Mid Feb 07)
• Problem Analysis and Methodology (1st March 07)
• Enhancement of CACTI (15th Apr 07)
• Validation against actual design (May 07)

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Current Status

• Initial Study and state of the art determination
  complete!
• Some of the problems have been identified
• First cut methodology is ready
• Following the methodology , replacement policy
  for LRU has been studied, estimated for power.

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Deliverable

• Model Implementation
• HDL for all the models of new architecture
  aspects
• Report on Methodology
• Final Report