Introduction%20

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Lesson 1

• Introduction Is there a limit?
• Transistors CMOS building blocks
• Physics, Cross section and Layout Views

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Is there a limit Moores Law
Intel co-founder Gordon Moore chuckled at those
who, in decades past, predicted the imminent
demise of Moore's Law. 1) This is the dictum
that resulted from his observation in 1965
that transistor density doubles every 18 months,
2) This pattern has held true to this day. 3)
Last year's semiconductor sales were 17 percent
of all electronics sales and 0.7 percent of
the gross world product 4) This percentage that
has risen slowly but steadily for 40 years. 5) A
generation from now, semiconductors will comprise
5.6 percent of the gross world product. 6)
It'll be at least a human generation before
Moore's Law begins to run out of gas at
around the 9nm.
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But
The traditional semiconductor chip is finally
approaching some fundamental physical limits. 1)
A gate oxide that is only three atoms thick
(_at_2007, 0.045um Intel) 2) Further innovation in
insulating materials. 3) Moore's Law, does not
apply to analog circuitry It might raise the
dynamic range of A/Ds by 1.5 dB per year but
the noise rises as chip area shrinks. 4)
Escalating cost of a semiconductor fab plant,
currently US3 billion per fab Also doubling
every three years. 5) Lithography. CMOS
structure, Interconnection, Power 6) "Life after
Moore" marked an end to the fascination with SoC
integration, beginning of
"dis-integration," separate amplifier
chips perform analog functions. 7) Moore's Law
projects a 59 percent per year increase in
transistor density, but processor packing is
only on a 15 percent per year. Human ingenuity
keeps shrinking the CMOS transistor, but with
increasingly expensive manufacturing
facilities.
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Silicon
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Lesson 2

• MOSFET I-V CHARECTARISTIC
• MOSFET I-V CHARECTARISTIC
• MOSFET IV Curves
• MOSFET Analog/Digital Models Propagation Delay

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MOSFET I-V CHARECTARISTIC
Lumped Analysis IDQN/Ttr Vdrift-mnEy-mn
(VD-VS)/L TtrL2/mnVDS QN QnWLCox(VG -
VT)WL IDSmn Cox W/L(VG-VT) VDS
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MOFET IV Curves
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Analog Modelgt Max Bandwidth
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Digital Modelgt Max Working frequency.
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Lesson 3

• Passive Elements
• The CMOS inverter A masterpiece

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Passive Elements
R rL / (tW) RRSQUAREL / W Cee0 / d
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A masterpiece

• Logic levels
• MOST a simple switch
• The CMOS inverter
• DC operation
• Dynamic operation
• Propagation delay
• Power consumption
• Layout
• Why is it better than others (Nmos,Bipolar)??

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CMOS logic 0 and 1

• Logic circuits process Boolean variables
• Logic values are associated with voltage levels
• VIN gt VIH ? 1
• VIN lt VIL ? 0
• Noise margin
• NMHVOH-VIH
• NMLVIL-VOL

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The MOST - a simple switch