Achieving Reliable Ultra LowPower Design with Aggressive Vdd Scaling

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Achieving Reliable Ultra Low-Power Design with
Aggressive Vdd Scaling

• Yu (Kevin) Cao, Huifang Qin, and Jan Rabaey
• YODA Group, BWRC, UC Berkeley

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Outline

• Ultra-Low Voltage (Vdd) Design
• Data Retention Voltage (DRV)
• 150mV SRAM Design
• Timing Variability
• A Self-Adaptive Approach at Ultra-Low Vdd
• Summary

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Energy Savings via Vdd Scaling
Data for 4-bit adder (130nm CMOS) obtained
using Monte-Carlo simulations.
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Ultra Low Voltage Design

• Vdd scaling
• Determined by both device and design specs.
• Most effective technique in power reduction

Ref Davrl, et al. Proc. IEEE, April 1995
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Price to Pay at Vdd lt300mV
Variability
Performance

• Data Preservation memory failure and instability

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Power vs. Reliability
New design methodologies that is
variation-tolerant
Logic
Vdd lt300mV
Real Bottleneck!
Unreliable storage
Memory
Vulnerability to soft errors
Circuit and architecture techniques to enhance
reliability
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Data-Retention Voltage (DRV) of SRAM
when VddDRV
DRV most sensitive to local mismatch!
VTC of SRAM Cell Inverters
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Analytical Model for DRV

• DRV degrades with local Vth mismatch
• Perfect SRAM cell DRV70mV
• w/ mismatch, DRV170mV

• DRV can be reduced by sizing up PMOS

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DRV Measurements
SRAM DRV test suite
Waveform of DRV measurement
(b) DRV 180mV in SRAM cell 2 with state 0
(a) DRV 190mV in SRAM cell 1 with state 1
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Spatial Distribution of DRV
256x128 Cells
90 Eleakage Saving
H. Qin, Y. Cao, D. Markovic, A. Vladimirescu, J.
Rabaey, Best Paper, ISQED 2004
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Further Reduction of DRV

• Sizing 3x PMOS size ? 30mV (50 area)
• Redundancy for systematic variations (e.g., row
  effect due to layout non-uniformity)

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ECC for Random Variations

• ECC (1 error out of 8bits ) 100mV reduction (50
  area)
• Together, DRV can be reduced to 150mV (from
  current 280mV).

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Excessive Timing Variance

• Timing variance increases dramatically with Vdd
  reduction
• Design for large yield means huge overhead at low
  voltages

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A Self-Adapting Approach

• Process variations is static, not dynamic
• Timing is controled by Vth tuning

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Vth Tuning via Body Bias
G
S
D
B

• Less design cost than Vdd tuning
• Vth tunable range 150-400mV for a 90nm Technology

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Power and Timing Tradeoffs
Vdd 200-500mV

• Vth tuning can effectively gain performance back

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The YODA Group

• Yield Optimization Design Approaches
• http//bwrc.eecs.berkeley.edu/research/YODA

Explore circuit, architecture, and design
strategies to achieve ultra low power consumption
and robust functionality for computing and
communication systems.
Jan Rabaey Andrei Vladimirescu Kevin
Cao Huifang Qin Ruth Wang Paul Friedberg Liang-Tec
k Pang Jonathan Tsao
Projects Ultra Low Voltage System Design Robust
Low Power Design Methodology Reliable SRAM
Leakage Reduction Reliable Model of Computation
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Summary

• Main challenges to ULV design
• Power, timing, and reliability tradeoffs
• SRAM DRV bottleneck of system voltage scaling
• A self-test, self-adapting approach
• Enhance system performance under variations
• Overarching goal of YODA
• Builde robust ultra-low power design