Design Methodology for FineGrained Leakage Control in MTCMOS

1
Design Methodology for Fine-Grained Leakage
Control in MTCMOS

• Ben Calhoun, Frank Honore, and
• Anantha Chandrakasan
• ISLPED, 2003

2
Outline

• Introduction
• Local vs Global Sleep Devices
• Sneak Leakage
• Local Sleep Regions
• Conclusion
• Questions

3
Multi-Threshold CMOS (MTCMOS)

• Low VT gates for SPEED
• High VT gates for LOW LEAKAGE

High VT has 10X/µm Lower Leakage than Low VT
Sleep
LOW VT LOGIC
HIGH VT Header and/or Footer
Sleep
4
Local vs Global Sleep Devices
Local
Global

• More Area
• Guaranteed Performance
• Standard Cells
• Active Leakage Savings

• Less Area
• Greater Savings in Full Sleep
• Degraded Noise Margins
• Difficult to Guarantee Performance
• Custom Design

5
Problem for Coarse-Grained Approach

• Wasted Active Leakage
• Idle Blocks have Low VT Leakage

Active
Sleep
Large Block
Local Blocks
Idle
Active Mode
Sleep Mode
6
Distributed Sleep Devices

• What about Local Sleep Devices?
• Break Up the Sleep FET

Active
Sleep
Idle
Active Mode
Sleep Mode
7
MTCMOS Granularity

• What about Local Sleep Devices?
• Move the FETs to LOCAL Blocks

Active
Sleep
Idle
Active Mode
Sleep Mode
8
MTCMOS Granularity

• What about Local Sleep Devices?
• Get ACTIVE Savings

Active
Sleep
Idle
Active Mode
Sleep Mode
9
Sneak Leakage

• sneak leakage (snek lekij) n. Any leakage
  current path from VDD to GROUND that draws high
  current relative to a cut-off path during Sleep
  Mode.

i.e. Current Path that Bypasses the Sleep
Device(s)!
10
Sneak Leakage is SNEAKY

• Possibly Data Dependent
• Span Hierarchical Levels

Works in Sleep Mode, Right?
Hierarchical Blocks
Low VT Adder On Critical Path
Low VT Comparison On Critical Path
High VT Circuit Off Critical Path
11
Sneak Leakage is SNEAKY

• Possibly Data Dependent
• Span Hierarchical Levels

Have to Look Inside Hierarchical Blocks
B
A
A XOR B
A
A
12
Sneak Leakage is SNEAKY

• Possibly Data Dependent
• Span Hierarchical Levels

Apply Sleep Is Everything Still OK?
B
A
A XOR B
A
A
13
Sneak Leakage is SNEAKY

• Possibly Data Dependent
• Span Hierarchical Levels

Look at A1 and B1. Still OK.
0
B1
A
A XOR B
A1
A
0
14
Sneak Leakage is SNEAKY

• Possibly Data Dependent
• Span Hierarchical Levels

Look at A0 and B1.
0
B1
A
A XOR B
A0
A
1
15
Sneak Leakage is SNEAKY

• Possibly Data Dependent
• Span Hierarchical Levels

Look at A0 and B1. Sneak Leakage!!
0
B1
A
A XOR B
A0
A
1
16
Sneak Leakage is Costly
100
215
Normalized Current
10
12
1
1
A1
A0, B as at right
A0, B forced to 0
17
Preventing Sneak Leakage

• Sneak Leakage Paths Occur at CMOS/MTCMOS
  interfaces
• More specifically, they occur where transmission
  gates form the CMOS/MTCMOS interface

18
Design Rules

• Any MTCMOS gate that shares an output with a CMOS
  gate or power rail needs to use both polarity
  sleep devices.
• An MTCMOS gate that shares outputs with other
  MTCMOS gates must use the same polarity sleep
  device(s) at the other gates.
• Any MTCMOS gate that shares a sleep device with a
  gate that uses both polarity sleep devices must
  also have (or share) both polarity sleep devices.
• Do not share sleep devices if the shared line
  creates a connection between outputs of multiple
  CMOS gates.

19
Design Rules

• Any MTCMOS gate that shares an output with a CMOS
  gate or power rail needs to use both polarity
  sleep devices.
• An MTCMOS gate that shares outputs with other
  MTCMOS gates must use the same polarity sleep
  device(s) at the other gates.
• Any MTCMOS gate that shares a sleep device with a
  gate that uses both polarity sleep devices must
  also have (or share) both polarity sleep devices.
• Do not share sleep devices if the shared line
  creates a connection between outputs of multiple
  CMOS gates.

1
0
20
Design Rules

• Any MTCMOS gate that shares an output with a CMOS
  gate or power rail needs to use both polarity
  sleep devices.
• An MTCMOS gate that shares outputs with other
  MTCMOS gates must use the same polarity sleep
  device(s) at the other gates.
• Any MTCMOS gate that shares a sleep device with a
  gate that uses both polarity sleep devices must
  also have (or share) both polarity sleep devices.
• Do not share sleep devices if the shared line
  creates a connection between outputs of multiple
  CMOS gates.

1
0
21
Design Rules

• Any MTCMOS gate that shares an output with a CMOS
  gate or power rail needs to use both polarity
  sleep devices.
• An MTCMOS gate that shares outputs with other
  MTCMOS gates must use the same polarity sleep
  device(s) at the other gates.
• Any MTCMOS gate that shares a sleep device with a
  gate that uses both polarity sleep devices must
  also have (or share) both polarity sleep devices.
• Do not share sleep devices if the shared line
  creates a connection between outputs of multiple
  CMOS gates.

1
0
22
Design Rules

• Any MTCMOS gate that shares an output with a CMOS
  gate or power rail needs to use both polarity
  sleep devices.
• An MTCMOS gate that shares outputs with other
  MTCMOS gates must use the same polarity sleep
  device(s) at the other gates.
• Any MTCMOS gate that shares a sleep device with a
  gate that uses both polarity sleep devices must
  also have (or share) both polarity sleep devices.
• Do not share sleep devices if the shared line
  creates a connection between outputs of multiple
  CMOS gates.

1
0
23
Design Rules

• Any MTCMOS gate that shares an output with a CMOS
  gate or power rail needs to use both polarity
  sleep devices.
• An MTCMOS gate that shares outputs with other
  MTCMOS gates must use the same polarity sleep
  device(s) at the other gates.
• Any MTCMOS gate that shares a sleep device with a
  gate that uses both polarity sleep devices must
  also have (or share) both polarity sleep devices.
• Do not share sleep devices if the shared line
  creates a connection between outputs of multiple
  CMOS gates.

1
1
1
24
Design Rules

• Any MTCMOS gate that shares an output with a CMOS
  gate or power rail needs to use both polarity
  sleep devices.
• An MTCMOS gate that shares outputs with other
  MTCMOS gates must use the same polarity sleep
  device(s) at the other gates.
• Any MTCMOS gate that shares a sleep device with a
  gate that uses both polarity sleep devices must
  also have (or share) both polarity sleep devices.
• Do not share sleep devices if the shared line
  creates a connection between outputs of multiple
  CMOS gates.

1
1
1
25
Design Rules

• Any MTCMOS gate that shares an output with a CMOS
  gate or power rail needs to use both polarity
  sleep devices.
• An MTCMOS gate that shares outputs with other
  MTCMOS gates must use the same polarity sleep
  device(s) at the other gates.
• Any MTCMOS gate that shares a sleep device with a
  gate that uses both polarity sleep devices must
  also have (or share) both polarity sleep devices.
• Do not share sleep devices if the shared line
  creates a connection between outputs of multiple
  CMOS gates.

1
1
0
1
26
Design Rules

• Any MTCMOS gate that shares an output with a CMOS
  gate or power rail needs to use both polarity
  sleep devices.
• An MTCMOS gate that shares outputs with other
  MTCMOS gates must use the same polarity sleep
  device(s) at the other gates.
• Any MTCMOS gate that shares a sleep device with a
  gate that uses both polarity sleep devices must
  also have (or share) both polarity sleep devices.
• Do not share sleep devices if the shared line
  creates a connection between outputs of multiple
  CMOS gates.

1
1
0
1
27
Subtle Paths Prevented on Chip
MUX
1
28
Subtle Paths Prevented on Chip
MUX
Applied RULE 1
1
29
Subtle Paths Prevented on Chip
MUX
1
0
1
Latch
30
Subtle Paths Prevented on Chip
MUX
1
0
1
Applied RULE 4
Latch
31
Testchip
CLBs

• 0.13µm, dual VT testchip
• High VT 100mV Low VT
• Low-Power FPGA Architecture
• 12 Configurable Logic Blocks (CLBs) in 3 slices
• lt 10 Delay Penalty from Fine-Grain Sleep Devices

Test And Scan
SLICE 2
SLICE 3
32
Results Oscilloscope Plot
8.2X
Sleep Asserted
7.0X to 8.6X measured savings for entire chip in
sleep mode
33
CLB Architecture
Sleep Regions take advantage of Fine-Grained
Sleep FETs
34
Sleep Region Interfaces

• Floating Nodes can cause Static Current
• Use Transmission Gates and Thoughtful
  Partitioning

Static Current!
Q
Q
Sleep Region Boundary
35
Sleep Region Interfaces

• Floating Nodes can cause Static Current
• Use Transmission Gates and Thoughtful
  Partitioning

Q
Q
Sleep Region Boundary
36
Results Sleep Region Active Savings
37
Conclusion

• Local Sleep FETs can work (7.0X to 8.6X measured
  leakage reduction)
• Design methodology prevents sneak leakage
• Local Sleep FETs give Active leakage savings
  (measured up to 2.2X)

38
Thank You
Any Questions?
Acknowledgements

• Cypress Semiconductor for chip fabrication
• Texas Instruments
• Infineon Fellowship
• DARPA