Yield Estimation based on Layout

1
Yield Estimation based on Layout Process Data

• by
• Karthik Subramanian
• Masters Thesis Work
• Mar 2003.

2
Contents

• Introduction to yield.
• Concept of critical area in ICs.
• Interconnect yield model.
• Yield estimation at the schematic stage.
• Yield estimation at the layout stage.
• Layout optimization for yield enhancement.

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Yield in the Semiconductor Industry

• Yield something yielded PRODUCT especially
  the amount or quantity produced or returned.
• Assessment of the quality of the design.
• Design for manufacturability (DFM).
• Manufacturability measure of the number of
  defect-free chips that can be produced from a
  single wafer1.
• Manufacturability M Nchip Y

Cchip Cwf/(Nchip Y)
4
Why DFM?

• DFM optimization of designs for maximum yield
  in the presence of contamination.
• (a). High wafer yield through contamination
  control has become difficult and hard to achieve.
  
• (b). Increase in fabless design houses, which
  have little control over the manufacturing
  process can control costs only by optimizing
  designs for higher yield2.
• Prediction of the IC area and yield is,
  therefore, critical to any sound IC design
  methodology.

5
Yield Loss in ICs

• Yield loss occurs when there is an unacceptable
  mismatch between the expected and actual
  parameters of an IC.
• Yield loss in ICs are classified into two types
• (a).Functional yield loss (Yfnc) due to spot
  defects (shorts opens).
• (b).Parametric yield loss (Ypar) due to global
  process disturbances.
• Defects circular disks of extra/missing material
  in any layer of the IC3.

Total Yield Yfnc Ypar
6
Critical Area in ICs

• The susceptibility of an IC layer to a defect is
  captured by the critical area function.
• The critical area for a defect of radius rd is
  defined as that area on a die where if the center
  of a circular defect falls, a fault occurs in the
  circuit3.

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Interconnect Yield Model

• The yield loss primarily takes place in the
  metals
• (a). The use of the metal layer is more
  extensive than that of any other layer in the IC.
• (b). The defect count is more in the metal
  layer.
• Poissons yield model Y exp(-AD)
• A die area D defect density.
• The interconnect yield Y of the chip5
• ACr critical area r0 defect radius r1
  half (the min. Spacing between metals) K and p
  are model parameters.

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Yield Estimation at the Schematic Stage

• Approximate value of the yield at the early stage
  of the design process.
• The Critical area is a function of the structural
  attributes of the circuit.
• Critical area can be calculated by extracting the
  structural parameters from the netlist of the
  circuit.

9
Yield Estimation at the Layout Stage

• Layout physical form of the design gives a
  realistic value of the yield.
• Use of Virtuoso-XL Layout editor to convert the
  circuit schematic to its layout, by placing cells
  and Autorouting the cells (Virtuoso Custom
  Router).
• Design of sample layouts using Virtuoso Layout
  editor.
• Extraction of Critical area using Cadence
  Dracula.
• Estimation of yield at the layout stage using
  the Interconnect yield model.

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Extraction of Critical Area for Shorts

• Step 1 Expand each geometry shape by radius R.  
• Step 2 Find the intersection area of such
  expanded geometry.  
• Step 3 Find the union of all intersection area.
   
• Step 4 Repeat steps 1, 2, and 3 for a range of
  defect sizes6.

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Extraction of Critical Area for Opens

• Step 1 Shrink both the edges of the conducting
  path by radius R extend the left and right edges
  of the shrunk conducting path by radius R.  
• Step 2 Shrink all edges of the rectangular
  contact by radius R.  
• Step 3 Find the union of the shrunk area.  
• Step 4 Repeat steps 1, 2, and 3 for a range of
  defect sizes4.

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Critical Area Extraction Using Dracula
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Critical Area in the IC Layout
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Yield Dependence on the Critical Area of an IC
15
Script for Yield Estimation at the Layout Stage
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Yield Enhancement by Layout Optimization

• Design of appropriate cells, that are small in
  size.
• Choosing smart place and route strategies/optimiza
  tion of wire spacing.
• (a). Additional Interconnect layers.
• (b). Reducing Cell Utilization.
• (c).Relaxing metal design rules7.

17
References

• 1 Heineken H.T., Khare J., Maly W., Yield
  loss Forecasting in the early phases of the VLSI
  design process, Custom Integrated Circuits
  Conference, Proceedings of the IEEE, 5-8 May
  1996, PP.27-30.
• 2 Heineken H.T., Khare J., dAbreu.M,
  Manufacturability Analysis of Standard Cell
  libraries, Custom Integrated Circuits
  Conference, Proceedings of the IEEE, 11-14 May
  1998, PP.321-324.
• 3 Heineken H.T., Maly W., Manufacturability
  Analysis Environment MAPEX, Custom Integrated
  Circuits Conference, Proceedings of the IEEE, 1-4
  May 1994, PP.309-312.
• 4 Ouyang C.H., Pleskacz W.A., Maly W.,
  Extraction of critical areas for opens in large
  VLSI circuits, Defect and Fault Tolerance in
  VLSI Systems, 1996 IEEE International Symposium
  on, pp.21-29.
• 5 Heineken H.T., Maly W., Interconnect Yield
  model for Manufacturability prediction in
  synthesis of standard cell-based designs,
  Computer-Aided Design, 1996, ICCAD-96. Digest of
  Technical Papers., 1996 IEEE/ACM International
  Conference on , 10-14 Nov 1996 , pp.368 373.
• 6 Nag P.K., Maly W., Hierarchical extraction
  of critical area for shorts in very large ICs,
  Defect and Fault Tolerance in VLSI Systems, 1995,
  Proceedings, 1995 IEEE International Workshop on,
  pp.19-27.
• 7 Ouyang C., Heineken H.T., Khare J., Shaikh
  S., d'Abreu M., Maximizing Wafer productivity
  through Layout optimizations, VLSI Design, 2000,
  Thirteenth International Conference on , 2000 ,
  pp. 192 197.
• http//www.uta.edu/icdesign/