Debugging on ARM Compatible Processors

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• Debugging on ARM Compatible Processors
• Shih-Chieh Tsai

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Outline

• Introduction
• Monitoring Techniques for RISC Embedded Systems
• ARMs Embedded ICE
• Future Work

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Introduction

• With advances of microprocessor design, what we
  think is not necessarily what we get.
• Focus on programming errors caused by designers.
  Other imperfection are not included, such as
  process variation, EDA tools bugs.

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Introduction (Contd)

• Monitoring is the extraction of information from
  a computational process.
• Process varies in at least 2 fields
• No. of pins.
• Time frame where measurements take place.

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Passive vs. Active Monitoring

• Passive monitoring data is observed, collected,
  and stored.
• Active monitoring data can be analyzed and we
  can take certain actions based on the analysis
  performed.

Data Acquisition Emulation and Analysis
Target System
Host Computer
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In-Circuit Emulators

• The most popular monitors for embedded systems.
• Help designers from software coding to HW/SW
  integration and final testing.
• Implemented by replacing the original processor
  with a test equipment incorporating an identical
  microprocessor prototype.
• Basic components probes, event filter, counters,
  memory circuit for buffering and control CKT.
• The ICE should not interfere the system being
  monitored.
• Disadvantage speed limit

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Logic Analyzers 1/2

• Passive hardware. It does not provide any control
  over the targeted processor.
• 2 purposes of using LA
• Analyzer the software.
• Verify data flow.
• Logic level vs. time values can be sampled at
  periodic intervals.
• Advantage
• Non-intrusive to SW and HW execution. Can execute
  real-time monitoring.
• Flexible. High speed LA can be configured for
  high speed processors where channel width can be
  traded for sampling speed.

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Logic Analyzers 2/2

• Disadvantage
• Passive monitors cant perform debug functions.
• LA is usually designed to work with only one
  processor.

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ARM's Embedded ICE Solution

• Advantages
• No pin count overhead.
• Low cost.
• Debug can be performed at full processor speed.
• Processor removal is not required.
• Requires no extra communication channel to debug.
  
• Works on any deeply embedded ARM system.

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Obstacles to Conquer

• High ability to observe the functionality of a
  processor in an embedded system.
• With clock rate exceeding 50Mhz, latching devices
  may be required to obtain meaningful data.

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System Components
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Future Work

• Based on jhwus ARM code, implement a debugging
  environment around it.
• For feasibility, tap out is necessary.
• Other peripheral circuits and programs.

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ARM7DI Core Architecture