P1251328617ehyHt

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Integrated Circuits Costs

• IC cost Die cost Testing cost
  Packaging cost
• Final
  test yield
• Die cost Wafer cost
• Dies per Wafer Die
  yield
• Dies per wafer š ( Wafer_diam / 2)2
  š Wafer_diam Test dies
• Die
  Area 2 Die Area
• Die Yield Wafer yield 1

???
Defects_per_unit_area Die_Area
?


Die Cost goes roughly with die area4
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Real World Examples

• Chip Metal Line Wafer Defect Area Dies/ Yield Die
  Cost layers width cost
  /cm2 mm2 wafer
• 386DX 2 0.90 900 1.0 43 360 71 4
• 486DX2 3 0.80 1200 1.0 81 181 54 12
• PowerPC 601 4 0.80 1700 1.3 121 115 28 53
• HP PA 7100 3 0.80 1300 1.0 196 66 27 73
• DEC Alpha 3 0.70 1500 1.2 234 53 19 149
• SuperSPARC 3 0.70 1700 1.6 256 48 13 272
• Pentium 3 0.80 1500 1.5 296 40 9 417
• From "Estimating IC Manufacturing Costs, by
  Linley Gwennap, Microprocessor Report, August 2,
  1993, p. 15

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Learning Curve

• When volume doubles, cost reduces 10
• Gordon Bell 1978
• Example PCs v. Workstations
• 1990 1992 1994 1997
• PC 24M 33M 44M 65M
• WS .41M .58M .68M .98M
• Ratio 59 57 65 67
• 65x 26 --gt .96 0.53

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Pipelining Its Natural!

• Laundry Example
• Ann, Brian, Cathy, Dave each have one load of
  clothes to wash, dry, and fold
• Washer takes 30 minutes
• Dryer takes 40 minutes
• Folder takes 20 minutes

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Sequential Laundry
6 PM
Midnight
7
8
9
11
10
Time
30
40
20
30
40
20
30
40
20
30
40
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T a s k O r d e r

• Sequential laundry takes 6 hours for 4 loads
• If they learned pipelining, how long would
  laundry take?

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Pipelined LaundryStart work ASAP
6 PM
Midnight
7
8
9
11
10
Time
T a s k O r d e r

• Pipelined laundry takes 3.5 hours for 4 loads

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Pipelining Lessons

• Pipelining doesnt help latency of single task,
  it helps throughput of entire workload
• Pipeline rate limited by slowest pipeline stage
• Multiple tasks operating simultaneously
• Potential speedup Number pipe stages
• Unbalanced lengths of pipe stages reduces speedup
• Time to fill pipeline and time to drain it
  reduces speedup

6 PM
7
8
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Time
T a s k O r d e r
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Computer Pipelines

• Execute billions of instructions, so throughout
  is what matters
• DLX desirable features all instructions same
  length, registers located in same place in
  instruction format, memory operands only in loads
  or stores

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Example MIPS ( DLX)
Register-Register
5
6
10
11
31
26
0
15
16
20
21
25
Op
Rs1
Rs2
Rd
Opx
Register-Immediate
31
26
0
15
16
20
21
25
immediate
Op
Rs1
Rd
Branch
31
26
0
15
16
20
21
25
immediate
Op
Rs1
Rs2/Opx
Jump / Call
31
26
0
25
target
Op
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5 Steps of DLX DatapathFigure 3.1, Page 130
Memory Access
Write Back
Instruction Fetch
Instr. Decode Reg. Fetch
Execute Addr. Calc
IR
L M D
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Pipelined DLX DatapathFigure 3.4, page 137
Instruction Fetch
Instr. Decode Reg. Fetch
Execute Addr. Calc.
Write Back
Memory Access

• Data stationary control
• local decode for each instruction phase /
  pipeline stage

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Visualizing PipeliningFigure 3.3, Page 133
Time (clock cycles)
I n s t r. O r d e r
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Its Not That Easy for Computers

• Limits to pipelining Hazards prevent next
  instruction from executing during its designated
  clock cycle
• Structural hazards HW cannot support this
  combination of instructions (single person to
  fold and put clothes away)
• Data hazards Instruction depends on result of
  prior instruction still in the pipeline (missing
  sock)
• Control hazards Pipelining of branches other
  instructionsstall the pipeline until the
  hazardbubbles in the pipeline

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