CoE EE 00142 Computer Organization Set 9 Memory

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CoE - EE 00142Computer OrganizationSet 9 Memory

• Ron Hoelzeman

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Five Computer Components
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Memory and Storage

• We have already seen memory
• Registers, program memory, etc.
• Lots of kinds
• Primary memory
• Cache
• Hard disks
• Removable disks, floppy
• Optical - CDROM
• Tapes
• etc.

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Memory Hierarchy
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Memory Hierarchy
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Basic Computer Organization
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Memory Hierarchy
Data typically transferred a block at a time
Fig 7.2
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Speed Size - Cost
Fig 7.1
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Memory Tradeoff
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Size Distance From CPU
Fig 7.3
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Example Memory Structure
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Internal Computer Memory

• Two basic styles - RAM and ROM
• RAM - Random Access Memory
• Read and Write
• ROM - Read Only Memory
• PLD, PLA, CPLD, FPGA

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Original Core Memory
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Properties of RAM Memory

• Static RAM - SRAM
• Essentially a latch or FF
• Dynamic RAM - DRAM
• Uses charge on capacitor
• Needs refreshing
• Both are volatile
• i.e. lose stored information when power is removed

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Main Memory Block Diagram
Graphics from Logic and Computer Design
Fundamentals, Mano Kime, Prentice Hall
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Example 1024X16 Memory
1024 x 16 words x bits
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Example Number Storage

• Suppose that we want to store the 32-bit
  hexadecimal value 12345678, and that it is to
  stored in a 32-bit word in byte-addressed memory
  starting in location 184. The word will require
  4 bytes with the least significant byte
  containing 78 and the most significant byte
  containing 12.

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Memory Data Byte OrderingThree Ways

• Little-endian
• Big-endian
• Bi-endian

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Byte Ordering Example
value 12345678
Little-endian
Big-endian
Intel x86, Vax
Motorola, Sun, RISC
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Bi-endian

• In a bi-endian machine, the data can be stored in
  either direction. The actual direction is
  determined by the operating system, but once
  established, all data is stored in the same
  direction.
• Power PC is example

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Memory Size

• Words or Bytes, typically bytes
• Measured in K, M, or G
• K - kilo - 210 1,024
• M - meg - 220 1,048,576
• G - gig - 230 1,073,741,824
• For example 64K 26 210 216

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Basic Static RAM Cell Model
Graphics from Logic and Computer Design
Fundamentals, Mano Kime, Prentice Hall
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RAM Bit Slice Model
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Fundamentals, Mano Kime, Prentice Hall
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Address Decoder
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Example Address Decoder
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RAM Bit Slice Model Symbol
Graphics from Logic and Computer Design
Fundamentals, Mano Kime, Prentice Hall
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16 - Word by 1 - Bit Chip
Graphics from Logic and Computer Design
Fundamentals, Mano Kime, Prentice Hall
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Three State Buffer
When EN 1, output input When EN 0, output
Hi Impedance
Allows you to connect 64K single bit
lines together without worrying about
loading Also allows connection to BUS
Graphics from Logic and Computer Design
Fundamentals, Mano Kime, Prentice Hall
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Consider a two dimensional memory selection
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16 X 1 RAM Using 4 X 4 Cell Array
Coincident Selection - use two k/2 input decoders
instead of one k input decoder
16 words by 1 bits but uses a row-column Coinciden
t Selection approach for addressing
Graphics from Logic and Computer Design
Fundamentals, Mano Kime, Prentice Hall
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Bit Plane Depiction of Memory
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8X2 RAM using 4X4 Cell Array
Can also be arranged in other ways Same 16 bits
but arranged 8 words by 2 bits using a
row-column approach for addressing
Graphics from Logic and Computer Design
Fundamentals, Mano Kime, Prentice Hall
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Coincident Selection

• Improves speed
• Reduces complexity
• Example - a realistic 32K X 8
• Single decoder 15 inputs 32K outputs would need
  32,800 gates
• With two decoders (6 and 9) would need 608 gates
• Reduces gates (therefore improves speed) by
  factor of 50

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64K X 8 RAM Chip
64K 216
Graphics from Logic and Computer Design
Fundamentals, Mano Kime, Prentice Hall
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256K X 8 RAM
256K 218
8 bit data
Graphics from Logic and Computer Design
Fundamentals, Mano Kime, Prentice Hall
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Alternatively - 64K X 16 RAM
16 bit data
Graphics from Logic and Computer Design
Fundamentals, Mano Kime, Prentice Hall
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RAM Conclusions

• Typically constructed in arrays
• Fabricated as chips
• Can be arranged in several forms
• Depending on machine configuration
• Main working memory of computer
• Used to hold programs and data

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Error Detection and Correction

• Used to check if data was written/read correctly
  - or if data is transmitted correctly
• Parity check - simplest
• even or odd
• Hamming code - more complex
• Detect and correct errors

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Even or Odd Parity

• 50/50 chance of detection
• Presumes one bit error most likely
• Detection only - no correction

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Even Parity Example
Data is on bits 1, 2, 3, 4, 5, 6, 7, 8
P XOR of bits (1, 2, 3, 4, 5, 6, 7, 8) 0 ? 1
? 1 ? 1 ? 1 ? 0 ? 0 ? 1 1
This is what is transmitted or stored
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Even Parity Example
If read correctly
P XOR of bits (1, 2, 3, 4, 5, 6, 7, 8, 9) 0 ?
1 ? 1 ? 1 ? 1 ? 0 ? 0 ? 1 ? 1 0
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Even Parity Example
If read incorrectly (error in bit 2 from a 1 to 0)
P XOR of bits (1, 2, 3, 4, 5, 6, 7, 8, 9) 0 ?
0 ? 1 ? 1 ? 1 ? 0 ? 0 ? 1 ? 1 1
But it is not clear where the error occurred
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Hamming Codes

• Error detection and correction
• Presumes one bit error most likely
• Detects error and position
• therefore allows for correction

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Hamming Code Example
Data is on bits 3, 5, 6, 7, 9, 10, 11, 12
P1 XOR of bits (3, 5, 7, 9, 11) 1 ? 1 ? 0 ? 0
? 0 0 P2 XOR of bits (3, 6, 7, 10, 11) 1 ?
0 ? 0 ? 1 ? 0 0 P4 XOR of bits (5, 6, 7, 12)
1 ? 0 ? 0 ? 0 1 P8 XOR of bits (9, 10, 11,
12) 0 ? 1 ? 0 ? 0 1
This is what is transmitted or stored
Note that parity bits are in power of 2 positions
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Hamming Code Example
If data received or read from memory is correct
4 check bits are evaluated as follows
C1 XOR of bits (1, 3, 5, 7, 9, 11) 0 ? 1 ? 1
? 0 ? 0 ? 0 0 C2 XOR of bits (2, 3, 6, 7, 10,
11) 0 ? 1 ? 0 ? 0 ? 1 ? 0 0 C4 XOR of bits
(4, 5, 6, 7, 12) 1 ? 1 ? 0 ? 0 ? 0 0 C8 XOR
of bits (8, 9, 10, 11, 12) 1 ? 0 ? 1 ? 0 ? 0 0
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Hamming Code Example
If data received or read from memory is not
correct
If read incorrectly (change bit 3 from a 1 to 0)
4 check bits are evaluated as follows
C1 XOR of bits (1, 3, 5, 7, 9, 11) 0 ? 0 ? 1
? 0 ? 0 ? 0 1 C2 XOR of bits (2, 3, 6, 7, 10,
11) 0 ? 0 ? 0 ? 0 ? 1 ? 0 1 C4 XOR of bits
(4, 5, 6, 7, 12) 1 ? 1 ? 0 ? 0 ? 0 0 C8 XOR
of bits (8, 9, 10, 11, 12) 1 ? 0 ? 1 ? 0 ? 0 0
0 0 1 1 Error in bit 3
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Programmable Logic Devices

• ROM - Read only memory
• PLA - Programmable logic array
• PAL - Programmable array logic
• CPLD - Complex programmable logic device
• FPGA - Field-programmable gate array

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Programmable Logic Devices

• All permanent
• Typically WORM
• write once - read many
• Typically use fuse, antifuse, or mask
• Sometimes erasable

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ROM - Read Only Memory

• Non volatile
• maintains information without power
• Typically programmed by
• blowing fuses
• masking
• Sometimes erasable - EPROM
• E2PROM electrically erasable

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Example ROM
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32 X 8 ROM Un-programmed
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Programmed ROM
Consider the above truth table or program
Note that this is how your BIOS is programmed
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Programmed ROM
Consider the above truth table or program
Note that A7 is 1 for combinations 0, 2, 3, 29
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Programmed ROM
Note that A7 is 1 for combinations 0, 2, 3, 29
Graphics from Logic and Computer Design
Fundamentals, Mano Kime, Prentice Hall
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Views of ROM

• Can be used to store program
• BIOS of computer
• Can be used as a combinational logic device

Note in previous example that A7 ?m (0, 2, 3,
29)
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Example ROM Logic Implementation

• Consider a circuit which inputs a 3-bit binary
  number and which generates a binary number equal
  to the square of that input number.

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Example Truth Table
Note output is square of input
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ROM Implementation
Graphics from Logic and Computer Design
Fundamentals, Mano Kime, Prentice Hall
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Views of ROM

• PROM - fixed ANDs and programmable ORs
• Used for sum of minterm implementations
• Example A7 ? m (0, 2, 3, 29)
• PAL - fixed ORs and programmable ANDs
• Used for product of maxterm implementations
• Example A7 ? M (1, 4, 5, 28, 30, 31)
• PLA - both ORs and ANDs programmable

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Configuration of PLD Devices
Graphics from Logic and Computer Design
Fundamentals, Mano Kime, Prentice Hall
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More Complex Devices

• VLSI Programmable Devices
• CPLDs - Complex programmable logic arrays
• FPGAs - Field programmable gate arrays
• Structure varies by manufacturer

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Memory Hierarchy - Disks, etc.
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Mass Storage Devices

• Typically involve physical motion
• Spin (disks) or slide (tape)
• Usually magnetic - hard disk, tape
• Sometimes optic - CDROM
• Involve three time-variables
• Seek time - to find track
• Latency time - to rotate to start of track
• Transfer time - to read/write data

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Disk Structure
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Typical Disk Layout
etc.
etc.
Typically tracks of data are buffered through a
disk cache
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Disk Storage Devices

• Transfer blocks of data or pages
• uses buffer or cache
• overlays blocks of main memory - pages
• appears as virtual memory
• Disk cache issues
• thrashing - program flips back and forth between
  data on two different pages

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Disk Cache Concepts

• Disk cache issues
• Thrashing
• Virtual Memory
• Pages - Memory Blocks
• Page faults

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Virtual Memory
Fig 7.20
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Virtual Memory Mapping
Fig 7.21
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Cache Memory

• Fast memory
• Resides between devices
• Main memory and CPU
• Hard disk and main memory (buffering of pages)
• Sometimes between main memory and screen

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Typical Memory Hierarchy
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Multiple Cache Hierarchy
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Cache Memory
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Locality of Reference

• When executing an instruction
• Most other program instructions are local
• Most instructions are sequential
• Most data is local
• Most data is stored together (array)
• Key aspect of cache

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Principle of Locality

• Spatial locality - if we got word i from memory,
  there is a good chance that we will want word i1
  soon
• Temporal locality - if we got word i once, then
  we will probably want it again, soon

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Principle of Locality

• Therefore, if we copy a block of words into cache
  when we need one (i i15), we will likely use
  several before we need to do another copy
• Eventually, we will have several non-contiguous
  blocks of memory in cache

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Example Cache Scheme
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Direct Mapped Cache
Note address 00000 011
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Direct Mapped Cache
mod 8 cache
upper 2 add bits become tag
Fig 7.3
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Direct Mapped Cache
Fig 7.7
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Fully Associative Cache
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Cache Concepts

• Cache hit - processor reads or writes data and
  finds it in cache
• Cache miss - not in cache
• must go back to main memory
• get whole block in process
• Data write
• write-through (both cache memory)
• write-back (only cache)

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Cache Memory
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Memory Speed - Cost
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End of Set