Design of a FaultTolerant CarryLookahead Adder

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Design of a Fault-Tolerant Carry-Lookahead Adder

• Chih-Yuan Huang, Tsung-Hsiu Ko, and Jiun-Lang
  Huang
• Graduate Institute of Electronics Engineering
• National Taiwan University

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Outline

• Introduction
• Proposed CLA-adder design
• Test pattern generator
• Area overhead
• Conclusion

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Introduction

• Addition is a basic operation in digital circuits
• Carry-lookahead adder is used in this project
• Purpose is to design a fault tolerant adder
• Support on-line testing
• Consider both single stuck-at faults and delay
  faults
• On-chip pattern generator
• Guarantee coverage level

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Previous works

• Input vector monitoring technique for concurrent
  BIST Voyiatzis 05
• On-line fault detection
• Fault detection in carry select adders Kumar 03
• The inherent duplicated structure
• Error correction by I/O inversion Oikonomakos
  06
• Fault tolerant re-computation

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Contribution

• 100 stuck-at and transition fault coverage is
  achieved at the sub-CLA-adders
• Simple pattern generator, no need to store the
  test response or signature
• Once a fault is detected, the controller can
  reconfigure the adder
• Limitation The adder performance is reduced by
  half in the on-line testing and reconfiguration
  mode

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Outline

• Introduction
• Proposed CLA-adder design
• Test pattern generator
• Area overhead
• Conclusion

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Conventional 64-bit CLA adder
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Objectives

• Support on-line testing
• Reconfigurable
• High test coverage
• Exploit the inherent structure
• Degrade performance to meet fault tolerance

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Block diagram of proposed design
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Functional mode
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Stuck-at fault testing mode (lower part)
comparator
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Stuck-at fault testing mode (upper part)
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Transition fault testing mode

• The configuration is the same as stuck-at fault
  testing
• The test pattern set is different

v1, v2
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Path delay testing mode
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Control signals

• Input
• E_lower, E_upper, E_delay error indication
• test start the test session. run stuck-at,
  transition, path-delay testing until the signal
  is deasserted
• rst reset the controller internal state (in case
  the fault is temporary)
• Output
• Error to indicate the input speed must be
  reduced
• mode control the input/output router signal
  redirection

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Fault tolerant reconfiguration

• Stuck-at fault or transition fault detected
• Use upper part or lower part for computation
• Path delay fault detected
• Allocate two cycles for each computation

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Fault tolerant reconfiguration
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Outline

• Introduction
• Proposed CLA-adder design
• Test pattern generator
• Area overhead
• Conclusion

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On-chip pattern generator

• Easy to generate
• Low area overhead
• High fault coverage
• Small test size
• Less important

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Stuck-at fault pattern set

• 100 coverage achieved
• Test size linear to the size of the CLA

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Transition fault pattern set

• For the n-bit CLA, 2n test vector pairs are
  needed

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Transition fault pattern set

• For the n-bit CLA, 2n test vector pairs are
  needed

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Pattern generator

• n-bit shift register and log(4n)-bit counter
• During 4n test cycles, both stuck-at and
  transition faults can be detected

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Outline

• Introduction
• Proposed CLA-adder design
• Test pattern generator
• Area overhead
• Conclusion

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Area overhead

• Synthesis tool Synopsys Design Compiler
• Cell library UMC 0.18 µm
• 75 overhead

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Outline

• Introduction
• Proposed CLA-adder design
• Test pattern generator
• Area overhead
• Conclusion

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Conclusion

• A fault tolerant CLA-adder is proposed
• Performance is degraded to support fault
  tolerance
• Stuck-at, transition and path delay faults are
  targeted
• 100 coverage can be achieved at CLA modules with
  the built-in pattern generator
• For a 64-bit CLA, the area overhead is 75

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Q A