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WCET Analysis for a Java Processor

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Martin Schoeberl. TU Vienna, Austria. Rasmus Pedersen. CBS, Denmark ... Martin Schoeberl WCET Analysis for a Java Processor. JTRES 2006 ... – PowerPoint PPT presentation

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Title: WCET Analysis for a Java Processor


1
WCET Analysis for a Java Processor
  • Martin Schoeberl
  • TU Vienna, Austria
  • Rasmus Pedersen
  • CBS, Denmark

2
Outline
  • Motivation
  • WCET analysis
  • The Java processor JOP
  • Results
  • Conclusion, future work
  • Demo

3
Motivation
  • Schedule analysis
  • For (hard) real-time
  • Execution time numbers needed
  • Static WCET analysis
  • No measurements!
  • Can not guarantee the WC
  • Still used

4
Issues with static WCET Analysis
  • Why is WCET Analysis so seldom used?
  • High-level part is easy
  • Low-level is the hard part
  • Instruction timing
  • Caches
  • Advanced, speculative processors

5
Static WCET Analysis
  • Mature research
  • High-level based in ILP
  • Construct CFG
  • Add execution time to BB
  • Build ILP equations
  • Sum of BB texe will be maximized
  • Frequency of in-edges out-edges
  • Add loop constraints

6
Low-level WCET Analysis
  • Execution time of basic blocks
  • Sum of instruction timing?
  • Not in modern CPUs
  • What about memory access?
  • Instruction cache
  • Instruction prefetch
  • Data cache
  • Very hard for general purpose CPUs

7
The Proposed Solution
  • Build a processor to simplify WCET Analysis
  • Avoid non analyzable features
  • Find better solutions
  • Java processor JOP
  • Built from ground up for WCET
  • FPGA implementation (small)
  • Not slow on average

8
JOP Features
  • A RISC stack machine
  • 4 stage pipeline
  • No dependencies
  • No shared state (e.g. memory)
  • Stack cache
  • Method cache

9
Size
Resource (LC) Memory (KB) Fmax (MHz)
JOP min. 1077 3.25 98
JOP typ. 2049 3.25 100
Lightfoot 3400 4 40
LEON3 7978 10.9 35
10
Performance
11
Low-level Timing
  • Bytecode execution time known
  • Analysis of microcode (DATE06)
  • No dependencies
  • Documented

12
Memory Access
  • Assume SRAM
  • Constant access time (rws and wws)
  • Access time partially hidden
  • Method cache load
  • Partially hidden

13
Method Cache
  • Full method loaded
  • Misses only on invoke/return
  • Cache contains several methods
  • Simpler to analyze
  • At call tree level
  • Other instructions are a hit

14
Method Cache Analysis
  • Only call tree leaves
  • Return is always a hit
  • Invoke in a loop
  • for (int i0 ilt10 i)
  • foo()
  • One miss and 9 hits
  • Miss times added to the CFG

15
Miss Times in the CFG
gt
16
Evaluation
Measured (cycle) Estimated (cycle) Pessimism (ratio)
Robot 736 775 1.05
Lift 7214 11249 1.56
Kfl 13334 28763 2.16
UdpIp 11823 219569 18.57
17
Conclusion
  • We need static WCET analysis
  • COTS processors dont work
  • Design HW for WCET
  • A RT computer architecture
  • JOP is a first step to RT processors
  • Analysis at bytecode level

18
Future Work
  • Method cache cont.
  • Detection of loop bounds
  • Integration into Eclipse
  • WC memory consumption

19
Demo Time
20
Thank You!
  • Questions
  • Suggestions
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