Sources of MOSFET Device Variation

1
Sources of MOSFET Device Variation
Random Dopant Fluctuation
National Technology Roadmap for Semiconductors,
SIA, 1997
2
System Under Consideration
H. O. Johansson and M. Horowitz, Sampling-Rate
Optimization of an Interleaved-Sampling Front
End, in Proc. IEEE Intern. Symp. on Circuit and
Systems, Piscataway, NJ, 2001, pp. 573-6.
3
Sampling Function
Why use sampling function? We dont have CAD
models for deep-submicron processes Matlab
analysis takes a lot less time (20 min.) than
Spice/Spectre (3 days)
H. O. Johansson and C. Svensson, Time Resolution
of NMOS Sampling Switches Used on Low-Swing
Signals, IEEE Journal of Solid-State Circuits,
vol. 33, no. 2, Feb. 1998, pp. 237-45.
Under certain conditions simple sampling circuits
(e.g. NMOS transistor / transmission gate) can be
viewed as linear, time-invariant systems. The
sampling function is essentially the impulse
response of the sampling system (mirrored in
time), i.e.
4
Robust Sampling Rate Optimization
5
Extreme Values of Device Parameters
Nominal parameter vector
Y
(yield)
1-Y
AL
KU
AU
W
W
KL
In the set AL (AU) we consider the worst-case
(best-case) sampling function in our
optimization. The result is a sufficient
(necessary) condition for the system to satisfy
both the eye opening/width and yield
requirements. The sufficient condition
corresponds to a lower bound and the necessary
condition corresponds to an upper bound.
6
Simulation Results
130nm 1-inch PCB trace 50 scaling increase
75nm 1-inch PCB trace 50 scaling increase
of samplers
of samplers
Clock Period (ns)
Clock Period (ns)
Transistor Width (um)
Transistor Width (um)
Nearly identical ! system is completely
dominated by jitter
An investigation of low-jitter PLL design is
important!
7
PLL Jitter Analysis
Jitter Noise Sources
M. Mansuri and C.-K. K. Yang, Jitter
Optimization Based on Phase-Locked Loop Design
Parameters, IEEE JSSC, vol. 37, No. 11, November
2002.
8
PLL Jitter Analysis
Noise Transfer Functions

• damping factor
• wN loop bandwidth

Output phase noise spectrum
Jitter
9
PLL Jitter Analysis
Robustness Issue Maximize the parameter region
for which the jitter is less than J0.
1. J. G. Maneatis, Design of High-Speed CMOS
PLLs and DLLs, in Design of High-Performance
Microprocessor Circuits, pp. 235-60. 2. J. A.
McNeill, Jitter in Ring Oscillators, IEEE JSSC,
vol. 32, No. 6, pp. 870-9, June 1997. 3. J. A.
McNeill, Jitter in Ring Oscillators, Ph.D.
Dissertation, Boston Univ., Boston, MA, 1994.
4. A. Hajimiri et al., Jitter and Phase Noise
in Ring Oscillators, IEEE JSSC, vol. 34, No. 6,
pp. 790-804, June 1999. 5. A. Hajimiri et
al., A General Theory of Phase Noise in
Electrical Oscillators, IEEE JSSC, vol. 33, No.
2, pp. 179-94, February 1998. 6. S.
Sidiropoulos et al., Adaptive Bandwidth DLLs and
PLLs Using Regulated Supply CMOS Buffers, 2000
Symposium on VLSI Circuits, pp. 124-7. 7. J.
G. Maneatis, Low-Jitter Process-Independent DLL
and PLL Based on Self-Biased Techniques, IEEE
JSSC, vol. 31, No. 11, pp. 1723-32, November
1996. 8. K. Lim et al., A Low-Noise
Phase-Locked Loop Design by Loop Bandwidth
Optimization, IEEE JSSC, vol. 35, No. 6, pp.
807-15, June 2000. 9. M. Mansouri et al.,
Jitter Optimization Based on Phase-Locked Loop
Design Parameters, IEEE JSSC, vol. 37, No. 11,
pp 1375-82, November 2002.