The Instruction Set Architecture Level

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The Instruction Set Architecture Level

• Dept. of Computer Science
• Virginia Commonwealth University

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ISA level
Backward compatible
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5.1. properties
Defined by how the machine appears to a machine
language programmer
Memory model, registers, data types and
instructions, etc
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5.1.2 Memory Models
Memory collection of addressable cells
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5.1.2 Memory Models
Aligned? Single Linear address space? Memory
semantics
Read/write Serialized/Sync instruction
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5.1.3 Registers
Registers visible to micro architecture
level Some are visible to ISA Level (\TOS, MAR)
special purpose (SP, PC)
control registers for kernel mode
PSW (Program Status Word)
condition codes (bits in PSW)
N,Z,V,C,A,P general
purpose (local variables, etc)

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5.1.3 Instructions
Load, store
Move
Arithmetic
Logic
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5.1.5 Pentium 4 ISA level
Level 0 kernel mode Level1 Level2 Level 4
User mode
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5.1.5 Pentium 4 ISA level
Main arithmetic register Good for holding
pointers Play a role in looping For and /
Pointer(M) to the source Pointer(M) to the
destination Base of current stack frame Stack
pointer
Segment registers
Instruction Pointer (PC) PSW
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5.1.6 UltraSPARC III ISA Level
RISC machine
Multiple GPRs set
32 64bit GPR and 32 bit floating point
registers FP Frame pointer SP stack
pointer CWP current window pointer
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Only STORE, LOAD can access memory
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5.1.6 UltraSPARC III ISA Level
8 Global registers
1. Emulate stack w/ Procedure call 2. Fast
parameter passing
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5.1.7 8051 ISA Level (embedded system)
One chip with CPU, memory and I/O controller
8 bit R0 to R7
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5.2 Data Types at the ISA level
,meaning data types supported by hardware
Numerical data types, (232-1, or 231-1, Non
numerical data types, Data types on the Pentium
4, SPARC and 8051
n f x 10e , fraction( or mantissa),
exponent 3.14 0.314 101 3.14
1000.000001 0.1 10-5 1.0 10-61941
0.1941 104 1.941 103
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5.2.1. Numerical data types
Integer( unsigned 232-1, or signed 231-1) n
f x 10e , fraction( or mantissa),
exponent 3.14 0.314 101 3.14
1000.000001 0.1 10-5 1.0 10-61941
0.1941 104 1.941 103
Real N continuum Floating P N 2 179100 1
Rounding (nearest number) 0.9998x1099 vs
0.999x1099
F 3 digit in the range of 0.1 lt f lt 1, e
zero and signed 2 digit
-0.999x1099, -0.100x10-99, 0, 0.100x10-99, 0.999
x 1099
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5.2.2. Nonumerical data types
ASCII(7) vs UNICODE(16) Boolean Machine address
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5.2.3. Pentium, Sparc, and 8051
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5.3. Instruction Format
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5.3.1 Design criteria for instructionFormats
Size of instruction? n-16 bit instruction vs n
-32 bit instruction Memory size, fetch speed vs
harder to decode, more time to decode and execute
Accommodate all the operation desired. 2n
operation with n-1 bit?
Size of address field? Memory (232 bytes) If 8bit
byte as a basic unit of word vs 32 bit word vs 1
bit (Burroughs B1700)
Resolutionshorter address means shorter
instruction vs. Waste space, Extra comparison
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5.3.2 Expanding Opcodes
(nk) bit instrcution If 2n memory cell, we have
only 2k opcodes
With 16 registers
What if we have15 three address instn, 14 two
address instn, 31 one address instn and 16 no
address instn? Size of instruction n-16 bit
instruction vs n -32 bit instruction Memory size,
fetch speed vs harder to decode, more time to
decode and execute
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5.3.2 Expanding Opcodes
We have variable size opcode to make the unit
size instructions. Variable size instruction is
hard to decode, even hard to align on byte
boundaries
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5.3.3. case studies
1,2,3 byte