Niranjan Soundararajan, Aditya Yanamandra,

1
Analysis and Solutions to Issue Queue Process
Variations

• Niranjan Soundararajan, Aditya Yanamandra,
• Chrys Nicopoulos, N. Vijaykrishnan,
• Anand Sivasubramaniam, Mary Jane Irwin
• Microsystems Design Laboratory (MDL)
• Computer Systems Laboratory (CSL)
• Computer Science and Engineering
• The Penn State University

2
Process Variation (PV) - Introduction
Process Variation Variation in characteristics
between two identically designed circuits
Process Variation
Dynamic
Static

• Aging
• Thermal Effects

Systematic
Random

• Sub-wavelength
• Lithography
• Overlay

• Dose
• RDF

J. Tschanz et al., DAC 2005
3
Process Variation - Impact
Performance impact Increase in number of
critical paths
Power Impact Increase in leakage power dissipation
Lack of predictability in timing characteristics
lead to loss of yield Economic impact is
significant
Definite need to address PV at circuit and
microarchitectural level
J. Tschanz et al., DAC 2005
4
Current solutions to address PV

• Global solutions
• Body Biasing
• Frequency boost increases leakage. Issue Queues
  high power density makes it non-ideal solution
• Time-borrowing
• Increases design complexity. Absorbing clock
  jitter and skew becomes difficult
• Structure-specific solutions
• Solutions for register file, and caches
• Issue Queue performance-determining structure,
• operation combines CAM, SRAM cells

5
Contributions

• Study the impact of PV on the Issue Queue of a
  microprocessor
• PV-unaware design has about 21 performance
  degradation
• PV is a non-deterministic phenomenon. Design-time
  static partitioning not possible. Our solution
  enables the fast and slow entries to co-exist
• Instruction steering and sub-component switching
  schemes are proposed to reduce the impact of PV
• Performance loss is about 1.3

6
Outline

• Motivation
• Contributions
• Issue Queue Overview
• PV Analysis of Issue Queue sub-components,
  activities
• Steering Mechanisms
• SpeedSteer, OptiSteer
• Intra-Entry Variations
• Operand- and Port-Switching
• Conclusion and Future Work

7
Pipeline Configuration
RAT
Op Oper1 STag DTag
Op Sreg1 Sreg2 Dreg
DTag
Reg
ROB id
Inst
Inst
Out-of-order Issue
In-order Dispatch
- - -
Fetch
Decode
ALU
Issue Queue
Result (Data)
Alloc
ISQ Entry Allocation
- - -
Oper1
Reorder Buffer (ROB)
- - -
ARF
8
Issue Queue
Issue Read
Tag1
Tag N
Forwarding Write
Forwarding Comparison
V
Opcode
R
Tag
Operand
R
Tag
Operand
Dest Tag
Select Logic
Dispatch Write
INSTRUCTION ISSUE
Valid Bit Reset
SELECT INST. READY
t
t1
t2
t3
Alloc stalls Dispatch
Time
ALLOC LOGIC
DISPATCH WRITE
Valid Bit Set
ISQ Full
FORWARDING
Instruction wait for Ready Operands
Operand Ready Bit Set
9
Simulation Setup

• Issue Queue size is 24 entries
• Circuit-level simulations done at 22nm
• HSPICE for circuit design using PTM device models
• Simplescalar modified to support PV
• SPEC2K benchmark suite

10
Performance Impact of PV on ISQ activities

• Issue Queue Activities
• Dispatch Write (Dw), Issue Read (Ir), Forwarding
  (Fw)
• Dependence between activities
• Slow Dispatch Write affects Forwarding (Tag
  comparisons)
• Slowing down any of the activities has equal
  impact on performance
• Biggest Impact when all three activities slow down

1.43
1.28
1.27
1.27
1.18
11
Variation Analysis of ISQ Components
CAM Match
SRAM Write
1 cycle
2 cycles
60
40
Variations
5 Gate Length 10 Threshold Voltage
ISSUE QUEUE
12
Outline

• Motivation
• Contributions
• Issue Queue Overview
• PV Analysis of Issue Queue sub-components,
  activities
• Steering Mechanisms
• SpeedSteer, OptiSteer
• Intra-Entry Variations
• Operand- and Port-Switching
• Conclusion and Future Work

13
Existing solutions to handle ISQ PV

• Shutting down slow entries
• Simple, 12 degradation
• MCD solution
• Switch between fast non-degraded small and slow
  degraded large ISQ
• 7.3 degradation in performance

1.43
1.33
1.26
14
PV Aware Instruction Steering SpeedSteer
Variation unAware
Forwarded Tag
ALLOC
Stall for additional cycle
Op STag1 STag2 DTag
1
RAT
DTag
1
0
Extra Forwarding Stalls Possible
ALLOC
Stall Dispatch
Aware of Variation
15
PV Aware Instruction Steering OptiSteer
Issue Queue
Op STag1 STag2 DTag
Dest Tag
Dest Tag
RAT
ISQ Entry id
STALL
- - -
Slow Entry Bit
Alloc
Decoder
Demux
- - -
Stall Optimization Table
Source Tags (STag1, STag2)
16
PV Aware Instruction Steering
1.43
1.36
1.31
1.14
17
Outline

• Motivation
• Contributions
• Issue Queue Overview
• PV Analysis of Issue Queue sub-components,
  activities
• Steering Mechanisms
• SpeedSteer, OptiSteer
• Intra-Entry Variations
• Operand- and Port-Switching
• Conclusion and Future Work

18
Intra-Entry Variations

• ISQ Entry has multiple sub-components
• SRAM and CAM cells
• Sub-components not used by every instruction
• Single Source operand
• Operand Ready at dispatch
• Random variations lead to varying operating
  speeds for different ports
• Different activities can operate at different
  speeds

65
47
33
26
17
Occurrence
Utilization
19
Operand- and Port-Switching
Issue Read
Op STag1 Operand1 STag2 DTag
V
Opcode
R
Tag
R
Tag
Operand
Dest Tag
Operand
Op STag2 STag1 Operand1 DTag
Dispatch
Dispatch Write
Operand Switch
Port Switch
Op STag1 Operand1 STag2 DTag
20
Timeline of activities
SELECT INST. READY
Port Switch
Slow issue read
SELECT INST. READY
Less instructions selected
INSTRUCTION ISSUE
Valid Bit Reset
t
t1
t2
t3
ALLOC LOGIC
Alloc stalls Dispatch
Time
DISPATCH WRITE
Valid Bit Set
Operand Switch
Port Switch
FORWARDING
Operand Ready Bit Set
ISQ Full
SOT Fill
Slow Dispatch Write
Instruction wait for Ready Operands
SOT Value Required Forwarding Stall
21
Steering with Operand and Port Switching
1.43
1.42
22
Conclusion and Future Work

• Process Variation plays a major role in future
• Impact of Random and Systematic variations
  increasing
• By tackling ISQ variations, the available slack
  could be used by solutions like time-borrowing
• Issue Queue is a complex pipeline structure
• Multiple issue queues designs exist
• Select logic PV need to be studied

23
Backup Slides
24
Port Switching
Bus Lines
NB
AB
NP
NP
AP
NP
NP - NonPV Port AP - Alternate Port NB - Bus
corresponding to NonPV Port AB - Bus
corresponding to Alternate Port
NB
AB
NP
Port Switching Logic
Cell Logic
25
Stalling implementation
Decoder
RAT
ISQ
Latch
Enable
Fl Mul
ROB
Alloc
Stall
Dispatch Stall
Latch
Enable
Resource Availability
Last Dispatch Slow
Fl Add
Forwarding Bus
Latch
Enable
Int Add
Select Logic

Issue Queue
SOT
Inst Ready
Port Assign
Slow Entry
Issue Stall
Forwarding Stall
26
Variation-Aware Testing

• Variation-aware schemes to identify critical
  paths are being proposed
• Vikram Iyengar et al., ICCAD 2007
• SRAM variation-aware testing can be applied for
  issue queue entries
• M. Tehranipour. ISCAS 2001
• Test patterns for variation-affected gates
• D. Arumí-Delgado et al., ETW 2003

27
Related Work

• S. Borkar et al., DAC 2003
• X. Liang, D. Brooks. MICRO 2006
• I. Kim, M. Lipasti. ISCA 2003
• E. Brekelbaum et al., MICRO 2002
• H. Ananthan et al., ISLPED 2004
• A. Tiwari et al., ISCA 2007
• J. Abella et al., IEEE Micro
• G. Semararo et al., MICRO 2002
• H. Jacobson. ISLPED 2004