Chapter 7: Parallel IO Ports

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Chapter 7 Parallel I/O Ports
Basic I/O Concepts
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Basic I/O Concepts
Peripheral devices (I/O Device) Pieces of
equipment that exchange data with a computer.
Examples include switches, light-emitting
diodes, cathode-ray tube screens, printers,
modems, keyboards, and disk drives. Interface
(peripheral) chip - A chip whose function is to
synchronize data transfer between the CPU and I/O
devices. - An interface may consist of control
registers, status registers, data
direction latches, and control circuitry. - An
interface chip has pins that are connected to the
CPU and I/O port pins that are connected to the
I/O devices. - Each interface chip has a chip
enable signal input or inputs, when asserted,
allow the interface chip to react to the data
transfer request. - Data transfer between an I/O
device and the CPU can be proceeded bit-by-bit
(serial) or in multiple bits (parallel).
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I/O Schemes 1. Isolated I/O scheme - The
microprocessor has dedicated instructions for I/O
operations - The microprocessor has a separate
address space for I/O devices 2. Memory-mapped
I/O scheme - The microprocessor uses the same
instruction set for I/O operations - The I/O
devices and memory components are resident in the
same memory space
Pros and cons
Traditionally, Intel microprocessors use the
isolated I/O method, whereas Motorolamicroprocess
ors use the memory-mapped I/O method. The 68HC11
microcontroller has no separate I/O instructions
and uses memory-mapped I/O exclusively.
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I/O Transfer Synchronization The role of an
interface chip 1. Synchronizing data transfer
between CPU and interface chip. 2. Synchronizing
data transfer between interface chip and I/O
device.
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Synchronizing the Microprocessor and the
Interface Chip The polling method 1. for input
-- the microprocessor checks a status bit of the
interface chip to find out if the interface
chip has received new data from the input
device. 2. for output -- the microprocessor
checks a status bit of the interface chip to find
out if it can send new data to the interface
chip. The interrupt-driven method 1. for input
-- the interface chip interrupts the
microprocessor whenever it has received new data
from the input device. 2. for output -- the
interface chip interrupts the microprocessor
whenever it can accept new data from the
microprocessor.
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Synchronizing the Interface Chip and the I/O
Devices Brute-force method -- useful when the
data timing is unimportant 1. for input --
nothing special is done. The microprocessor
reads the interface chip and the interface chip
returns the voltage levels on the input port pins
to the microprocessor. 2. for output -- nothing
special is done. The interface chip places the
data that it received from the microprocessor
directly on the output port pins. The strobe
method -- a strobe signal is used to indicate
that data are stable on I/O port pins 1. for
input -- the interface chip latches the data into
its data register using the strobe signal. 2. for
output -- the interface chip places the data on
port pins that it received from the
microprocessor and asserts the strobe signal.
The output device latches the data using the
strobe signal. This method can be used if the
interface chip and I/O device can keep up with
each other. The handshake method -- used when
timing is crucial - two handshake signals are
used to synchronize the data transfer. One
signal, call it H1, is asserted by the interface
chip. The other signal, call it H2, is asserted
by the I/O device. - two handshake modes are
available -- pulse mode and interlocked mode.
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Handshake Method

• The Brute-force method and the strobe method
  cannot guarantee correct data transfer between an
  interface ship and an I/O device
• Consider the case of a printer. It takes much
  longer time to have a character printed than it
  does to send a character to the printer
  electronically.
• The solution use a handshake protocol
• Two handshake methods interlocked and
  pulse-mode
• Two handshake signals are needed H1 is asserted
  by the interface chip and H2 is asserted by the
  I/O device

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Input Handshake Protocol Step 1. The interface
chip asserts (or pulses) H1 to indicate its
intention to input data. Step 2. The input device
puts data on the data port pins and also asserts
(or pulses) the handshake signal H2. Step 3.
The interface chip latches the data and
de-asserts H1. After some delay, the input
device also de-asserts H2.
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Output Handshake Protocol Step 1. The interface
chip places data on the port pins and asserts (or
pulses) H1 to indicate that it has valid data to
be output. Step 2. The output device latches the
data and asserts (or pulses) H2 to acknowledge
the receipt of data. Step 3. The interface chip
de-asserts H1 following the assertion of H2. The
output device then de-asserts H2.
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• 68HC11 Parallel I/O Overview
• - The 68HC11A8 has 40 I/O pins that are arranged
  in five I/O ports.
• - All I/O pins serve multiple functions.
• - Ports A, B, and E with the exception of port A
  pin 7 are fixed-direction inputs or outputs.
• - Ports C and D are bi-directional I/O pins under
  the control of their associated data
• direction registers.
• - Port C, port B, the STRA pin, and the STRB pin
  are used for strobed and handshake
• parallel I/O, as well as for general-purpose
  I/O.
• Port Registers
• Each I/O port has a data register associated with
  it, except port C
• To input, the 68HC11 reads from the port data
  register
• -To output, the 68HC11 writes into the port data
  register
• PORTA (at 1000)
• PORTB (at 1004)
• PORTC (at 1003)

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Fixed Direction I/O (ports A, B, and E) To input
from an input port, execute a load instruction
with the port data register as the source
operand. For example, the following instruction
sequence reads a byte from port
E REGBAS equ 1000 I/O register block base
address PORTE equ 0A offset of port E data
register from REGBAS ldx REGBAS ldaa PORTE,X
To output a byte to an output port, write to the
port data register directly. For example, the
following instruction sequence outputs the value
38 to port B REGBAS equ 1000 I/O register
block base address PORTB equ 04 offset of port
B data register from REGBAS ldx REGBAS ldaa
38 staa PORTB,X
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• Bi-directional I/O (Ports C and D)
• - Each pin of ports C and D has an associated bit
  in a specific data register and another in a
• data direction register.
• - The primary direction of a pin is set by its
  associated bit in the data direction register.
• - The data direction registers are cleared by
  reset to configure all bi-directional I/O pins
  for
• input.
• To configure a bidirectional I/O pin for
  input, set the associated direction bit in the
  datadirection register to 0.
• To configure a bidirectional I/O pin for
  output, set the associated direction bit in the
  data direction register to 1.
• - Before performing I/O operation to these two
  ports, the software should set up the
• data direction registers of these two ports.

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Example 7.1 Write an instruction sequence to
output the value CD to port D. Solution REGBAS
equ 1000 PORTD equ 08 DDRD equ 09 ldx REGBAS
ldaa 3F set up the directions of port D
pins staa DDRD,X ldaa CD output CD
to port D staa PORTD,X In C language,
DDRD 0x3F / configure port D for output
/ PORTD 0xCD / output data to port D /
1009 is the address for the data direction
register for Port D (called DDRD)
bit5
bit0