M-CORE%20Introduction

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M-CORE Introduction

• Topic Overview
• Comparison to Comp-Arch 1 topics
• Register Files
• Execution / Function Unit Elements
• Instruction Set / Execution
• Core Implementation
• General Implementation
• MMC2001
• Other MCUs
• ARM7
• THE PIC!!!!!!

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Embedded Processors

• Embedded vs. Desktop Processors
• Advantages
• Lower cost
• Optimized Instruction Set
• Lower Power consumption
• Smaller footprint
• Disadvantages
• Slower clock speeds
• Less Processing power

• Applications
• Embedded Processors
• Cell phones / pagers / PDAs
• DAQ
• Controls (Automotive, Industrial)
• Smart Media
• Desktop Processors
• Desktop computers
• Notebook computers / Laptops

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Overview
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Register File

• User Programming Model
• 16 X 32 bit General Purpose Registers
• 32 bit Program Counter (PC)
• Carry Flag (C Bit)
• Supervisor Programming Model
• 16 X 32-bit alternate register file
• Processor and Global status registers (PSR/GSR)
• Vector base register (VBR)
• Exception saved Special Function Registers
• Five 32-bit supervisor scratch registers
  (SS0-SS4)
• Global Control Register (GCR)

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Register File - Continued
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Execution Unit Elements

• Hardware
• 32 bit ALU
• 32 bit Barrel Shifter
• Support Hardware for Multiplication

• Performance
• All instructions executed in single cycle except
• Multiply
• Unsigned Divide
• Signed Divide

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Instruction Execution

• 4 level pipeline
• Instruction Fetch
• Instruction Decode / Reg File Read
• Execute
• Reg File Write

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Instruction Set Overview

• Instruction Types
• Data
• Byte / Bit Manipulation
• Logical
• Shifts (Rotates)
• Load and Store
• Control
• Conditional
• Arithmetic
• Special

Monadic Instruction Format
Dyadic Instruction Format
Examples ABS (Absolute Value Monadic) XOR
(Exclusive OR Dyadic)
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Exception Processing

• Exception Types
• Reset
• Misaligned access
• Access error
• Divide by zero
• Illegal instruction
• Privilege violation
• Trace
• Breakpoint
• Unrecoverable error
• Soft reset
• Interrupt
• Fast interrupt
• Hardware accelerator
• Trap instructions

• Exception Handling
• Save PSR and PC to shadow registers (FPSR / FPC
  for fast interrupts, EPSR / EPC for all others)
• Determine Vector Number of Exception
• Determine Address of the First Instruction of
  Exception and Pass Control to Handler, Load PC
  and PSR with new values

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Special Features

• Power Management
• Power Saving Instructions WAIT, DOZE, and STOP
• Compact die (2.2 mm2)
• Minimized Logic and Routing Capacitance
• Gated Clocks
• Effective access to Internal and External Memory
• Hardware Accelerator Interface (HAI)
• Support for task acceleration by external
  hardware
• Data is Transferred between core and accelerator
  block by appropriate interface
• Acceleration blocks may be a counter, high speed
  multiply/accumulate or data encryption
• Debug Interface
• M-CORE Supports on chip emulation (OnCE) allowing
  a user to examine registers, memory or on-chip
  peripherals

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Implementation
M-CORE More then just a CPU core MLB M-CORE
Local Bus PIG Peripheral Interface Gasket PIG
Bus Peripheral Bus MIG Module Interface
Gasket EIM External Interface Module PIE PIG,
Interrupt Control, EIM MIM M-CORE Integration
Module
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ImplementationMMC2001

• MMC2001 Includes
• M-CORE 32 Bit Processor
• 256 K-Byte ROM
• 32 k-Byte SRAM with battery backup support
• External Interface Module
• 20 Address / 16 Data Lines
• Timer/Reset Module
• Time of Day timer
• Watchdog Timer
• Reset unit
• 2 Independent UART Modules
• 6 Independent PWM Modules
• Serial Peripheral Interface (SPI) Bus
• OnCE Debugger Module

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M-CORE Key Advantages

• High Code Density
• 30 less memory than most 32 bit CPUs
• Low Power
• 1.8 to 3.6 V currently
• 0.9 V near future
• Several peripherals on chip
• Easy interface form the core to
• communication hardware
• memory

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M-CORE Disadvantages

• Compared to other embedded processors, M-CORE
  really isnt all it is hyped up to be!
• Motorola support is very poor
• Difficult to navigate website
• Poor documentation
• Motorola development tools are non-existent (or
  hard to find) Very poor selection
• MMC2001
• MMC2107
• Most features M-CORE prides itself on are
  Future developments

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M-Core Compared - ARM
M-CORE ARM
Data Size 32 Bit 32 Bit
Speed 50 MIPS 130 MIPS
Size 2.2 mm2 .59 mm2
Power Consumption .41mW/MHz .25mW/MHz
Register File 16 GP Registers 16 GP Registers
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M-Core Compared - PIC
M-CORE PIC
Number of Devices 2 Nearly 100
Speed 50 MIPS 10 MIPS Today 30 MIPS Future
Footprint 144 Pin QFP 8 Pin (DIP or SOIC) up to 80 Pin QFP
Comments Difficult to navigate documentation, Poor customer service Easy to navigate, Good customer service
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M-Core Compared - PIC
M-CORE (MMC2107) PIC (PIC18F458) dsPIC (dsPIC30F6014)
Data Size 32 Bit 8 Bit 16 Bit
Speed 31 MIPS 10 MIPS 30 MIPS
ROM 128K X 8 16K X 16 144K
RAM 8K X 8 1.5K 256 EEPROM 8K 4k EEPROM
Peripherals 10 bit ADC WDT SPI/SCI 10 bit ADC WDT UART/SPI/CAN 2.0 10 bit ADC WDT UART/SPI/I2C/CAN/ AC97/I2S
Package 144 QFP 44 QFP 80 QFP
Clock input 0 33 MHz 0 40 MHZ 0 10 MHZ
Cost 30.00 10.00 Future Product
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QUESTIONS?
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References
http//www.motorola.com/SPS/MCORE/ http//www.digi
key.com http//www.arm.com/armtech/ARM7_Thumb?Open
Document http//www.microchip.com/1010/index.htm M
icrochip Technologies 4th Quarter 2001 Product
Line Card