Design Review

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Design Review 2
Team 1 Cowboy and Indians
March 22nd, 2005
Mark Hairgrove
Jay Patel
Prameet Shah
Samir Shah
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1. Results of Design Exploration

• We were looking at various components we could
  implement.
• Database Storage Media
• HMAC with MD5 Authentication
• We were deciding between real time and post
  signal processing.
• We were considering 3 different potential
  architectures for the design of our system
• NIOS Arbiter
• Dual ARM
• Dual ARM, Split Database

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Results of Design Exploration
Database Storage Media

• No one has been able to properly implement the
  SDRAM on the NIOS.
• Other media is available, ie. secure digital (SD)
  and smart media.
• SD and smart media requires data to be sent in
  packets requiring more overhead. Cannot use DMA
  in both these media.
• Compact flash allows us to use DMA, and can be
  easily connected with ARM (only uses 15 GPIOS).
  Its access times (read100ns ) arent too high,
  avoiding latency.

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Results of Design Exploration
HMAC with MD5 Authentication

• HMAC with MD5 is not difficult
• to code
• C implementations already exist!
• MD5 computation is fairly fast
• 5 ms on a 10 KB message
• MD5 offers good authentication, unlike the
  generic hash we were considering
• Used in real world security applications

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Results of Design Exploration
Real-time vs Post Signal Processing

• Ideally, its always good to processing a signal
  once you captured all of it.
• There might not enough onboard memory.
• Delays the the processing time.
• If we have interrupts, why should we post
  process. REAL-TIME PROCESSING
• Between interrupts, we can apply filters to the
  smalls section of input data. This way we
  minimize idle time of DSP processor. We just have
  to be careful that we dont miss any interrupts.
• This allows the DSP to deliver the proper
  nucleotides sequences to the NIOS as fast as
  possible.

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Results of Design Exploration

• Design 1 NIOS Arbiter

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Results of Design Exploration

• Design 1 NIOS Arbiter

• Issues
• We have a clear load imbalance with this design
  (ARM will be on vacation most of the time)
• Implementing BLAST across NIOS and ARM is
  complicated
• Have to transfer a lot of data to the ARM (in the
  end, the ARM will see every DB string)
• SDRAM doesnt work

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Results of Design Exploration

• Design 2 Dual ARM

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Results of Design Exploration

• Design 2 Dual ARM

• Issues
• Memory transfers to the ARM are slow as they have
  to go through the NIOS as an intermediary.
• Synchronizing the memory is difficult to
  implement and even harder to make fast.
• We need a ton of I/O to the NIOS (approx 53).

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Results of Design Exploration

• Design 3 Dual ARM, Split Database

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Results of Design Exploration

• Design 3 Dual ARM, Split Database

• Issues
• Increased complexity of the system
• We need a ton of I/O to the NIOS (approx. 51
  general purpose I/Os)

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2. Final Design Overview

• There are some clear advantages with the third
  design.
• Parallelism Two ARMs are faster than one
• Minimized amount of data transfer between ARM and
  NIOS
• Centralized BLAST algorithm

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Design Exploration
BLAST Algorithm
94.2
4.8
0.9
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Final Design

• but we still have issues to deal with
• Not enough I/Os on NIOS
• Solution combine ARM data lines with SRAM
  address lines
• We never communicate with the ARM and the SRAM at
  the same time
• We can switch GPIOs on the ARM to be inputs on
  the fly (prevent from driving lines)
• Address lines for SRAM are always inputs

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Final Design

• Design 4 Master/Slave Dual ARM

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3. Implementation Plan 2.0
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4. Current Status
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5. Verification Test Plan

• We will test our system on two levels unit and
  system
• Server, Network and Distributed Nodes
• This will be tested with a series of nodes that
  are simulated in software
• Custom Hardware
• Test with verilog testbench in ModelSim and cross
  reference with MATLAB
• BLAST Algorithm
• Test with a sequence of test vectors
• Memory
• Test with programs that erase, write and read
  from memory

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6. Demo 2 Plan/Deliverables

• BLAST Algorithm on NIOS Interfaced with SRAM
• Get BLAST code working on the NIOS using DB on
  SRAM
• Test and prove correctness
• Master/Slave ARM BLAST Algorithm
• BLAST Algorithm working in parallel with
  hard-coded databases
• Communication protocol established, implemented,
  tested
• Client/Server Software
• Server software working without authentication
• Tested through simulated nodes
• DSP
• Convert analog signals to digital signals.
• Store data on DSP and start applying filters (low
  pass and band pass)

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7. Schedule
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7. Schedule
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Questions?