Cost Criteria

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Lecture 5 EGR 270 Fundamentals of
Computer Engineering
Reading Assignment Chapters 2-3 in Logic and
Computer Design Fundamentals 4th Edition by Mano

• Cost Criteria
• We need some sort of measure that will indicate
  how efficiently logic expressions can be
  implemented. Two methods are presented in the
  textbook
• 1) Literal cost
• 2) Gate input cost
• Literal Cost
• The literal cost is defined as the number of
  literal appearances in a logic expression. A
  literal is any complemented or uncomplemented
  variable.
• Example
• F AB CD CE Literal cost __________
  
• Number of gates _______
• F AB C(D E) Literal cost __________
• Number of gates _______

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Lecture 5 EGR 270 Fundamentals of
Computer Engineering

• Literal cost is easy to calculate, but doesnt
  always represent circuit complexity well. In the
  following example, the literal cost is the same,
  but the number of gates required to implement the
  functions is quite different.
• Example
• F ABCD ABCD Literal cost __________
  
• Number of gates _______
• F (AB)(BC)(CD)(DA) Literal cost
  __________
• Number of gates _______
• Gate Input Cost
• Gate input cost is simply the number of inputs to
  all gates if the implementation corresponds
  exactly to the expression given. Note that input
  inverters are typically not counted as inputs are
  often available in complemented or uncomplemented
  form.
• Gate input cost is a good measure for
  contemporary logic implementations since it is
  proportional to the number of transistors and
  wires used in implementing a logic circuit.
• For the previous example, gate input cost is
  perhaps a better measure of circuit complexity.
  (Draw each circuit to clearly show the gate input
  cost.)
• Example
• F ABCD ABCD Gate input cost __________
  
• F (AB)(BC)(CD)(DA) Gate input cost
  __________

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Lecture 5 EGR 270 Fundamentals of
Computer Engineering

• Multiple-Level Circuit Optimization
• Recall that SOP and POS expressions are both
  two-level circuit implementations. Although
  these implementations may result in the shortest
  propagation delay, other implementations may have
  lower gate input cost.
• Example (Refer to Figure 2-26 from the text
  shown below)
• G ABC ABD E ACF ADF ? see Fig a below.
  Gate input cost ______
• G AB(CD) E AF(CD) ? see Fig b below.
  Gate input cost ______
• G (ABAF)(CD) E ? see Fig c below. Gate
  input cost ______
• G A(BF)(CD) E ? see Fig d below. Gate
  input cost ______

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Lecture 5 EGR 270 Fundamentals of
Computer Engineering
Transformations for Multiple-Level Circuit
Optimization As seen in the last example, the
circuit cost can sometimes be reduced through
algebraic manipulation (or transformations). As
with Boolean algebra, there are no specific rules
for these transformations, but five types of
transformations can be defined as follows

• Factoring finding a factored form of a SOP or
  POS expression
• Decomposition expression of a function as a set
  of new functions
• Extraction expression of multiple functions as
  a set of new functions (decomposing multiple
  functions to extract common subexpressions)
• Substitution substituting function G into
  function F is when F is expressed as a function
  of G and some or all of the original variables of
  F
• Elimination the inverse of substitution in
  which function G in an expression for function F
  is replaced by the expression for G. Elimination
  is also called flattening or collapsing.

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Lecture 5 EGR 270 Fundamentals of
Computer Engineering
Example - Factoring Reduce circuit cost through
factoring for the function G below G ACE
ACF ADE ADF BCDEF Original
expression Gate input cost ________ Number of
gate delays ________ Factored expression Gate
input cost ________ Number of gate delays
________
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Lecture 5 EGR 270 Fundamentals of
Computer Engineering
Example - Decomposition Function G was factored
in the previous example as follows G ACE
ACF ADE ADF BCDEF G A(CD)(EF)
BCDEF Now introduce two new functions, X1 and
X2 (note their complements) X1 CD X2 E
F Next rewrite G in terms of X1 and X2 (i.e.,
decompose G in terms of X1 and X2). Draw the
circuit also. G Original expression Gate
input cost ________ Number of gate delays
________ Factored expression Gate input cost
________ Number of gate delays
________ Decomposed expression Gate input cost
________ Number of gate delays ________
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Lecture 5 EGR 270 Fundamentals of
Computer Engineering
Example - Extraction Extraction is the process of
decomposing multiple expressions to extract
common subexpressions. First consider the
original expressions for functions G and H G
ACE ACF ADE ADF BCDEF H ABCD
ABE ABF BCE BCF (expression in the text
is incorrect) Next factor the functions as
follows G A(CD)(EF) BCDEF H B(ACD
(AC)(EF)) Now introduce three new functions,
X1, X2 and X3 as follows X1 CD X2
E F X3 A C Next extract X1, X2
and X3 from G and H (see circuits on the
following two pages) G H Original
expressions for G and H Gate input cost
________ Expressions for G and H with X1, X2 and
X3 extracted Gate input cost ________
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Lecture 5 EGR 270 Fundamentals of
Computer Engineering
Original expressions for functions G and H (label
the output of each gate) G ACE ACF ADE
ADF BCDEF H ABCD ABE ABF BCE
BCF
Original expressions for G and H Gate input cost
________
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Lecture 5 EGR 270 Fundamentals of
Computer Engineering
Reduced expressions for G and H using extraction
(label the output of each gate) X1 CD
X2 E F X3 A C G AX1X2
BX1X2 H B(AX1 X3X2) BAX1 BX3X2
Reduced expressions for G and H Gate input cost
________
End of Test 1 material
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Lecture 5 EGR 270 Fundamentals of
Computer Engineering

• Chapter 3 Combinational Logic Design
• Chapters 1-2 covered the basic tools for working
  with combinational logic circuits, including
• number systems
• Boolean expressions
• Minimization techniques
• Logic gates
• Chapter 3 introduces topics related to the design
  of combinational logic circuits, including
• design procedure
• hierarchical design
• common combinational logic circuits/functions,
  including
• encoders, decoders, priority encoders
• multiplexers, de-multiplexers
• magnitude comparators
• BCD to 7-segment decoders

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Lecture 5 EGR 270 Fundamentals of
Computer Engineering

• Types of logic circuits
• There are two broad types of logic circuits
• 1) Combinational logic circuits
• circuits whose outputs are determined by logic
  operations on the input values
• Chapters 1-5 deal with combinational logic
  circuits

• 2) Sequential logic circuits
• circuits that include memory devices (such as
  flip-flops) as well as combinational logic so
  that the outputs are based on both present and
  past inputs
• Sequential logic circuits are introduced in
  Chapters 6

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Lecture 5 EGR 270 Fundamentals of
Computer Engineering

• Design Hierarchy
• It would be almost impossible to design a complex
  system by connecting one logic gate at a time.
• A divide and conquer approach is used to break
  the circuit into blocks.
• Interconnected block form the entire complex
  circuit.
• Large blocks can be broken into smaller blocks.
• Each block must have carefully defined functions
  and interfaces.

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Lecture 5 EGR 270 Fundamentals of
Computer Engineering
Figure 3-2 Design Hierarchy and Reusable Blocks
This design approach is referred to as a
hierarchical design.
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Lecture 5 EGR 270 Fundamentals of
Computer Engineering

• Figure 3-3 Hierarchy for Figure 3-2
• The figure below shows the structure of the
  hierarchy without the interconnections.
• The structure has the form of an upside down
  tree with the leaves on the bottom.
• Figure 3-3a shows each block and we see that 32
  NAND gates are required.
• Figure 3-2b is more compact and only shows one
  copy of each distinct block.
• The NAND gates in this case are pre-defined
  circuits and are referred to as primitive blocks.
• Complex structures may have other predefined
  blocks that have no logic schematics.
• Functional blocks will later be introduced that
  are predefined reusable blocks providing many
  basic functions used in digital design. Tool
  libraries are often available containing widely
  used functional blocks.
• In any hierarchy, the leaves consist of
  predefined blocks, some of which may be
  primitives.