Retiming%20with%20Interconnect%20and%20Gate%20Delay

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Retiming with Interconnect and Gate Delay

• CUHK CSE CAD Group
• Dennis Tong
• 29th Sept., 2003

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Presentation Outline

• Retiming Revisit
• Retiming with Interconnect Delay
• Future Work
• Conclusion

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Retiming

• Problem Formulation
• given a sequence circuit G(V, E, d(v), w(euv)),
  retiming can be viewed as an vertex-to-integer
  mapping, r V ? Z, where Z is the set of integers
  such that a new circuit G(V, E, d(v), wr(euv))
  is obtained.

wr(euv) w(euv) r(v) r(u) ? 0
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Retiming with Interconnect Delay

• Two Algorithms Proposed
• an optimal approach
• gives optimal solution when both gate and
  interconnect delay are considered
• a near-optimal fast approach
• gives optimal solution when gate delay is
  neglected, but still gives near-optimal results
  when both delays are considered
• runs much faster

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An Optimal Approach

• Extension from the Original Paper
• Retiming Synchronous Circuitry, Charles E.
  Leiserson and James B. Saxe, Algorithmica,
  65-35, 1991.
• Main Idea
• transform retiming to a special case of MILP
  which is polynomial time solvable

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Near-optimal Fast Approach

• give optimal solution when no gate delay
• Pre-processing
• replace each gate by a wire
• represent gate delay d(v) by wire delay d(v1,v2)

pre-process
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Near-optimal Fast Approach

• Post-processing
• remove registered got retimed into the gates
• use linear programming to minimize clock

post-process
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Near-optimal Fast Approach

• Algorithm Overview
• transform G(V,E) into a DAG G(V,E)
• construct timing constraints
• solve the set of constraints
• find optimum Topt by binary search
• post-process flip flops got retimed into gates

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Near-optimal Fast Approach

• Step 1 Transform G(V,E) into a DAG G(V,E)
• traverse G in a depth-first manner
• break all back edges found
• denote Vb the set of vertices have back edges
  (e.g., A and B ? Vb)

DFS traversal
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Near-optimal Fast Approach

• Step 2 Define Timing Variable tv

tv - for all v ? V, denotes the maximum
interconnect delay from a register
connecting to an input of v.
In general, tv is given by tv ? max tu
d(u,v) ? (w(euv) r(v) ? r(u)) T
u ? in(v)
in(v) the set of vertices in V with an edge
pointing to v in G
tc MAX tc1 , tc2 tc1
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Near-optimal Fast Approach

• Step 2 Construct Timing Constraints

Given tv for all v ? V tv ? max tu
d(u,v) ? (w(euv) r(v) ? r(u)) T (1)
u ? in(v)
We have constraints tv ? T ?v ? V
(2) tv ? tv ?v ? Vb (3) r(v)
r(v) ?v ? Vb (4)
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Near-optimal Fast Approach

• Step 3 Solve the Set of Timing Constraints
• Main Idea

Express tv for ?v ? V in terms of tu and r(u)
where u ? Vb
Reduce the constraints involve tu and r(u) only
Use Bellman-Ford algo. to solve for tu and r(u)
Derive tv and r(v) by propagating tu and r(u) in
G
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Near-optimal Fast Approach

• Step 3 Express tv in terms of tu and r(u) where
  u ? Vb

?uv - for all u, v ? V denotes the maximum delay
among all the directed paths from u to
v in G when no retiming is done,
reducing the delay by T if a register is
encountered.
For example, ?AA max dABCA 5T , dACA
3T ?AB max dABCB 4T , dACB 2T
Combining tv and ?uv, (1) becomes tv ? max
tq ?qv ? (r(v) ? r(q)) T (1)
q ? anc(v)
anc(v) the set of vertices in Vb with a
directed path to v in G
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Near-optimal Fast Approach

• Step 3 Reduce the constraints involve tu and
  r(u) only

Given tv for all v ? V tv ? tq ?qv ? (r(v)
? r(q)) T ?q ? anc(v)
Let ?v tv r(v) T for ?v ? Vb, the constraints
become ?q ?qv ? ?v (5) ?q ?qv ? ?v (6)
A system of difference inequalities
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Near-optimal Fast Approach

• Step 3 Derive tv and r(v) from tu and r(u) in G

Solve ?u for ?u ? Vb by Bellman-Ford algo.
Compute tu and r(u) given ?u tu r(u) T
Compute tv and r(v) for ?v ? V - Vb using (1)
Step 4 Find optimum Topt by binary search
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Experimental Results - I

• Testing Environment
• Intel Xeon 1.8GHz, 512KB cache, 512MB RAM
• ISCAS89 suite

NEAR-OPTIMAL NEAR-OPTIMAL OPTIMAL OPTIMAL T Topt Topt ()
Circuits V E T runtime (sec) Topt runtime (sec) T Topt Topt ()
s1488 655 1405 18.85 0.28 18.82 5.62 0.16
s1494 649 1411 20.78 0.25 20.78 4.37 0.00
s3271 1574 2707 10.24 1.09 10.24 33.70 0.00
s3330 1791 2890 27.05 0.50 27.05 43.14 0.00
s3384 1687 2782 24.21 0.74 24.16 25.19 0.21
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Experimental Results - II
NEAR-OPTIMAL NEAR-OPTIMAL OPTIMAL OPTIMAL T Topt Topt ()
Circuits V E T runtime (sec) Topt runtime (sec) T Topt Topt ()
s4863 2344 4093 23.58 3.12 23.58 87.75 0.00
s5378 2781 4261 27.27 1.16 27.25 138.68 0.07
s6669 3082 5399 23.07 1.91 22.96 177.59 1.00
s9234 5599 8005 42.73 4.08 42.73 512.86 0.00
s13207 7953 11302 72.34 8.11 72.34 1161.07 0.00
s15850 9774 13794 67.82 24.02 67.82 1545.59 0.00
s38417 22181 32135 36.53 83.56 36.52 7680.79 0.03
s38584 19255 33010 94.26 445.63 N/A gt15000 --
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Future Work

• Multi-pin Net Handling
• find a maximum sharing of flip flops in a net
  while the clock is preserved
• avoid unrealistic increase in number of flip
  flops

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Future Work

• Circuit Delay Modeling
• flip flop positions affect delay estimation
• load in each branch affect one another