The BaBar Silicon Vertex Tracker (SVT)

1
The BaBar Silicon Vertex Tracker (SVT)

• Claudio Campagnari
• University of California
• Santa Barbara

2
Outline

• Requirements
• Detector Description
• Performance
• Radiation

3
SVT Design Requirements (TDR)

• Performance Requirements
• Dz resolution lt 130 mm
• Single vertex resolution lt 80 mm.
• Stand-alone tracking for PT lt 100 MeV/c.

• PEP-II Constraints
• Permanent dipole (B1) magnets at /- 20 cm from
  IP.
• Polar angle restriction 17.20 lt Q lt 1500.
• Must be clam-shelled into place after
  installation of B1 magnets
• Bunch crossing period 4.2 ns (nearly
  continuous interactions).
• Radiation exposure at innermost layer (nominal
  background level)
• Average 33 kRad/year.
• In beam plane 240 kRad/year.
• SVT is designed to function in up to 10 X
  nominal background.

4
SVT characteristics

• Five layers, double sided (R? and z)
• Barrel design, L4 and 5 not cylindrical
• 340 wafers, 6 different types
• Low mass Kevlar-Carbon Fiber support ribs
• Upilex fanouts to route signal to ends
• Double-sided AlN HDI (104 of these)
• Outside tracking volume
• Mounted on Carbon Fiber cones (on B1 magnets)
• Atom chips
• 1156 chips, 140K channels

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Space Frame and Support Conesmounted on B1
magnets
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Layer 1,2,(3) vertexing Layer (3),4,5 tracking
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SVT Modules
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SVT High Density Interconnect
Flexible Tail (testing version)

• Functions
• Mounting and cooling
• for readout ICs.
• Mechanical mounting point
• for module.

Berg Connector
Mounting Buttons
AToM Chips

• Features
• AlN substrate.
• Double sided.
• Thermistor for temp. monitor.
• 3 different models.

Upilex Fanout
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Silicon Wafers

• Features
• Manufactured at Micron.
• 300 mm thick.
• 6 different wafer designs.
• n- bulk, 4-8 kW cm.
• AC coupling to strip implants.
• Polysilicon Bias resistors on wafer, 5 MW.

• Bulk Properties
• Bias current 0.1 to 2.0 mA
• Bulk current 0.1 to 2.0 mA
• Depletion voltage 10 to 45 V

• Strip
  Properties
• n-side n-side n-side p-side
• Strip Pitch 50 mm 55 mm 105 mm 50 mm
• Inter-strip C 1.1 pF/cm 1.0 pF/cm 1.0 pF/cm 1.1
  pF/cm
• AC decoupling C 20 pF/cm 22 pF/cm 34 pF/cm 43
  pF/cm
• Implant-to-back C 0.19 pF/cm 0.36 pF/cm 0.17
  pF/cm
• Bias R 4 to 8 MW 4 to 8 MW 4 to 8 MW 4 to 8 MW

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Silicon Wafers
P-stop
Edge guard ring
n Implant
55 mm
p Implant
Polysilicon bias resistor
Bias ring
Al
50 mm
Polysilicon bias resistor
Edge guard ring
p strip side
n strip side
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The AToM Chip
Custom Si readout IC AToM A Time Over threshold
Machine
5.7 mm

• Features
• 128 Channels per chip
• Rad-Hard CMOS process (Honeywell)
• Simultaneous
• Acquisition
• Digitization
• Readout
• Sparsified readout
• Time Over Threshold (TOT) readout
• Internal charge injection

8.3 mm
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The AToM Chip
Sparsification Readout Buffer
Chan
CAC
TOT Counter Time Stamp
PRE AMP
15 MHz
Shaper
Comp
Buffer
Si
Revolving Buffer 193 Bins
Event Time Event Number
Thresh DAC
Buffer
CAL DAC
CINJ
Serial Data Out

• TOT, Tstamp, Buffering
• 4 bits TOT (logarithmic)
• 5 bits Hit Tstamp
• (67 ns/count)
• 4 buffers / channel

• Amp, Shape, Discr, Calib
• 5-bit CAL DAC (0.5 fC/count)
• 5-bit Thr DAC (0.05 fC/count)
• Shaping time 100 - 400 ns
• Typical threshold 0.6-0.9 fC

• Trigger Latency Buffer
• 15 MHz Sample rate
• Total storage 12.7 us

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Performance

• Calibration, Noise
• Occupancy
• Efficiency
• Intrinsic Resolution

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Calibration

• Noise, gain, pedestals, bad channels obtained
  from scanning threshold with and without charge
  injection and counting hits
• 600K errfun fits, 150K linear fits
• once a day takes 2 minutes
• Very stable
• Downloadable chip parameters have not changed
  between Oct 1999 and 2004
• needed to change because of rad damage

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Alignment a curiosity

• SVT tied to machine elements, not to DCH
• SVT is always moving w.r.t. BaBar due to e.g.
  thermal excursions.
• Position of SVT as rigid body is monitored and
  fed back to reconstruction every hour

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Noise
1 MIP at normal incidence, about 23,000 electrons
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Cluster efficiency
e 97 (SW HW)
Excluding malfunctioning readout sections
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Resolution
Blue data Red MC
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Standalone reconstruction of low PT tracks
Reconstruction of ps from D ? D ps is (mostly)
with SVT alone
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Most of the detector is working

• Redundancy built in, e.g., 2 data and control
  paths
• Chips are only active electronics that is not
  accessible
• Layer 1 perfect
• 4/208 sections not working
• Problems are from
• shorts on hybrids
• elec. probems on wafers

21
Radiation

• Monitored by 12 diodes
• at radius of layer 1
• Diodes can abort beam
• Operation tricky due to
• heavy radiation damage
• Now also use diamonds

SVTRAD System
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Measured absorbed Dose
non-midplane
midplane
Few MRad in the horizontal plane Mostly from
showers from off-momentum beam particles Not
from Physics
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Consequences of high doses

• Bulk damage to Si
• increase ILEAK ? increase in noise
• type inversion
• Damage to chips
• originally tested to 5 MRad with Co source

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Bulk Damage
from Moll
Damage effectiveness ?
NIEL scaling high energy electron
cause significant damage (1/10 of hadrons) Not
appreciated by us originally
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Tests at Elettra (Trieste)

• C-2 vs V curve show inversion
• Results in agreement with
• NIEL scaling hypothesis
• Charge-collection-efficiency after
• local type inversion measured OK

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Expected Atom Chip Damage

• Radiation damage on AToM chip
• studied using Co60 sources at LBL and SLAC, up
  to 5 MRad.
• No digital failures (if chip power on)
• Gain loss 4.2 / MRad
• Noise increase 19/MRad

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Unexpected Phenomenon Pedestal Shift

• Pedestal (Threshold offset) started to increase
• Behavior associated with AToM chip location, not
  with strip location
• Remember we have 1 pedestal value per chip!!!

Chip 4
HDI Card in horizontal plane
Pedestal
Threshold offset (counts)
Channel
20 threshold DACs 1fC
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Pedestal Shift (cont.)

• Sets in at an integrated radiation dose of 1 Mrad
• But then it recovers.
• Effect reproduced at Elettra
• Ride out the storm by adjusting thresholds as
  well as we can

AToM Chip
narrow e- beam
2 Mrad
1 Mrad
Groups of 8 channels
Threshold offset (counts)
Delta Threshold (counts)
Effect reproduced _at_ Elettra
Integrated Radiation
Channel
Pedestal recovers
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Unexpected PhenomenonLeakage Current Increase

• Since May 2004 an anomalous increase in the bias
  current for some modules has been observed
• Only Layer-4 modules
• not a simple radiation damage effect
• No geometrical correlation
• Consequences
• increasing occupancies
• Coincides with beginning of "trickle injection"
  operation
• beam always on!!!!!

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Leakage Current Increase

• Hypothesis
• Accumulation of static charge on the silicon
  surface. The charge is beam-induced drifts
  because of the field between the facing sides of
  different layers.
• Causes increase in electric field at junction
• edge, inducing a soft junction breakdown.

-20V
20V
Pside
E
-20V
Nside
20V
Pside
Nside
DVL5-L440V
ILeak (?A)
By varying the potential drop across the air
between the layers we can control the effect
1800 0000 0600 1200
Solution change relative voltages, L4 vs
L5 Also, increase humidity of air
Time (hrs)
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Conclusions

• BaBar SVT has been working well for about 7 years
  now
• Installed and cabled in April 99
• Taking physics quality data since June 99
• There have been a few surprises along the way,
  but we have managed to survive