NetworkFlow Based HighLevel Power Optimization in VLSI Design

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Network-Flow Based High-Level Power
Optimizationin VLSI Design

• ???, ???
• KAIST, ????

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Nand gate behavioral, transistor, layout
O lt NOT ( A1 AND B1)
Boolean Equation
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Adder behavior, netlist, transistor, layout
Behavioral model
Structural model
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SoC System on a chip (beyond Processor)

• The 2001 prediction SoCs will be gt 12M gates

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ASIC synthesis flow
input
X
m
m
-

O
R
input
X
Clk
. . . .
output
Enable
. . . .
. . . .
algorithmic representation
RTL representation
logic-level representation
transistor-level representation
(out a(i) b(i) - c d(k) f)
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Synthesis flow
tree-height reduction arithmetic optimization
module implementation
RTL synthesis optimization
Target (cell) library
Architectural transformation
Sequential synthesis optimization
Combinational synthesis optimization
Scheduling
Binding
Determine latency and resources (rough)
registers, functional units, muxes, buses
two-level, multi-level optimization
FSM generation
retiming
Design constraints and objectives area, delay,
power consumption, testability.
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Bus-based Architecture
Typical Architecture Model
Register File
Functional Unit
Functional Unit
Functional Unit
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Power dissipation in CMOS
Vdd
(bad)
pMOS
0-gt1-gt0-gt1-gt0-gt0
x
x
0-gt0-gt0-gt1-gt1-gt1
C
(good)
nMOS
dynamic power CV2 f
Vss
CMOS inverter
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Power dissipation on Bus
1
8
0
1
transitions
00110011 -gt 00110010 -gt 11001101 -gt 11001101 -gt
11001111
data transitions on bus 1
bus1
Register File
Functional Unit
Functional Unit
Functional Unit
Minimizing switching activity !!!
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Example Design

• DFG
• 5 add. operations

• HW constraint
• Adders 2
• Bus line 4

Example DFG
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Scheduling Data transfers
clock step 1
clock step 2
e
f
c
d
a
b
1
3
2
clock step 1 a, b, c, d clock step 2 x, y, e,
f clock step 3 d, z
d
y
x
z
4
5
clock step 3
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Example Total Switching

• After scheduling and bus binding

Scheduled DFG
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Example Total Switching (2)

• Result by brute-force scheduling and binding

Scheduled DFG
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Example Bus Rebinding

• Result by bus rebinding

Scheduled DFG
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Example Rescheduling

• Result by rescheduling (move)

Scheduled DFG
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Previous Work (1)

• Network flow method
• Chang and Pedram
• Application
• Register allocation and binding DAC-95
• Functional unit binding EDAC-96
• Aspects
• Optimal solution
• Schedules not considered

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Previous Work (2)

• Power consumption on bus
• Dasgupta and Karri ISLPED-95, TCAD-98
• Aspects
• Minimize transitions of values on bus
• Combined scheduling and binding
• Method
• Simulated annealing process

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Our Work
Chang Pedram
Dasgupta Karri
optimal binding for a fixed schedule
scheduling binding
Our Work
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Motivation

• Slight change of schedule
• gt Big impact
• Repeated changes of schedule
• Find best binding for each schedule
• Need fast processing for binding

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Formulation for Bus-binding

• Adaptation
• Chang and Pedram
• Bus-binding problem
• gt Network flow problem

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Example
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Example (2)
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Network Flow

• Flow
• Definition
• A path from source to sink
• Meaning
• Value transitions on a bus
• (Total Flow) ( Bus Line)

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Network Flow (2)

• Min-cost flow problem
• Bus-binding minimizing switching
• Solution
• Polynomial time
• NP-Hard (Multi-Commodity)
• NP-Hard
• Inter-loop data transitions
• Invalid flows

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Example (3)
A flow
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Example (4)
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Initial Binding

• Idea
• Go around NP-Hardness
• Concept
• Resolve Invalid flows by pair-wise validation

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Example
Invalid flow
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Example (contd)
Pair of invalid flows
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Example (contd)
Validation
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A Move

• Definition
• Reschedule an operation
• By 1 clock step before or after
• Evaluation
• Bus-binding for each move
• Calculate SW
• Fast finding bus-binding

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Rebinding

• Choice 1 Apply full network flow
• Choice 2 Change the previous flow solution
  (minimally)
• Baseline Both must ensure the optimality of
  binding solution for the reschedule.

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Choice 2

• Step 1 max-flow computation
• - Rectify the flow paths of
• the previous schedule (should be
  fast)
• Step 2 min-cost computation
• - Use existing min-cost flow technique

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Step 1 Example
Initial Flow
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Rescheduling
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Local Graph
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Apply Min-Cost max-Flow algorithm
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Update the Global Flow by replacing the solution
of local part
Guarantee Maximum flow, but may not be Minimum
cost
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Max-Flow of Min-cost Algorithms

• Minimum cost augmentation method(Ford-Fulkerson)
• repeat residual graph -gt min-cost
  augmenting path
• Cannot fit into our incremental network
  optimization
• framework.

2. Cost reduction method Given a maximum
flow, push as much flow as possible along a
negative cost cycle in residual graph
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Example
Initial Flow
5.0
a
c
d
1.5
2.2
1.6
2.0
b
e
5.5
flow cost 2.2 1.5 5.5 9.2
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Residual Graph
5.0
a
c
d
-1.5
-2.2
1.6
2.0
b
e
-5.5
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Negative Cost Cycle
5.0
a
c
d
-1.5
-2.2
1.6
2.0
b
e
-5.5
cycle cost 5.0 1.5 1.6 5.5 2.0 2.2
-0.6
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Updated Flow
5.0
a
c
d
1.5
2.2
1.6
2.0
b
e
5.5
new flow cost 5.0 2.0 1.6 8.6
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Experimental Results (1)
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Experimental Result (2)
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Experimental Results (3)
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Conclusion