Integrated Regulation for Energy-Efficient Digital Circuits

1
Integrated Regulation for Energy-Efficient
Digital Circuits

• Elad Alon1 and Mark Horowitz2

1UC Berkeley 2Stanford University
2
Scaling and Supply Impedance

• CMOS scaling led to lower supply voltages and
  constant (or increasing) power consumption

Impedance Requirements of High-Performance
Processors

• Forces drastic drop in supply impedance
• Vdd ?, Idd ? ? Zrequired ??
• Todays chips
• Zrequired 1 mO!
• Hard to achieve across a broad frequency range

• Required Impedance (O)

Technology (µm)
3
Power Distribution and Regulation

• Significant resources spent to meet impedance
  requirement
• Active regulation can be used to reduce impedance
• E.g., Active/switched decoupling

• But, these regulators increase total power
• Prevents adoption in todays power-limited chips

4
Power-Neutral Regulation
Vdd

• Gate delay depends on Vdd
• So Vdd needs to be greater than some Vmin
• Supply variations force higher nominal voltage
• Causes extra power dissipation

Vnom
Vmin

• Goal make regulator power less than power
  recovered from lower noise

5
Outline

• Regulator Topology
• Regulator Design
• Experimental Verification
• Conclusions

6
Linear Regulators
Series Regulator
Chip
-
Vdd
Load
Vreg

Vref

-
Shunt Regulator
Chip
-
Load
Vdd
Vreg

Vref

-
7
Series Regulator Efficiency
Vdd
Vref
Vdd
Noise
Vreg
Vdrop
Vreg
Load

• Clearly wont meet efficiency goal
• Regulator doesnt really change noise on Vdd
• So still need same margin
• But added an extra Vdrop from variable resistor

8
Shunt Regulator Efficiency
Itotal
max(Inoise)
Iload
Ishunt
max(Inoise)
0

• Regulator can only pull current out of supply
• Need to burn significant static current to
  counter noise in both directions
• Again, clearly inefficient
• Need to allow shunt to deliver energy to the load
• Not just dissipate it

9
Push-Pull Shunt Regulator
Vshunt
Ipush
Iload

Vreg
-
Vref
Ipush
Ipull

Load
-
Ipull
0

• Use an additional, shunt supply to push current
  into Vreg
• Regulator capable of countering large variations
• But regulator loss set mostly by average
  variation
• Similar to Active Clamp for board VRMs
• Build on previous work to improve on-die impedance

A.M. Wu and S.R. Sanders, An Active Clamp
Circuit for Voltage Regulation Module (VRM)
Applications, Transactions on Power Electronics.
Sept. 2001.
10
Outline

• Regulator Topology
• Regulator Design
• Shunt Supply Network
• Minimizing Static Power
• Experimental Verification
• Conclusions

11
Regulator Design Challenges

• Vshunt is not free
• Takes resources away from main supply
• Increases loss

• Need to minimize quiescent output current
• Otherwise regulator too inefficient
• Need GHz bandwidth feedback path
• With minimum feedback circuit power
• Output stage in particular is challenging

12
Shunt Supply Resource Allocation

• Finite number of pins, metal lines for power
• Need to allocate resources between main and shunt
  supplies
• For resistive losses
• If ensure that Vshunt only handles transients
• Resistive losses of main supply not heavily
  affected

13
Quiescent Output Current

• Went to push-pull topology to minimize quiescent
  current
• But many designs have significant Istatic
• To ensure output devices are off when Vreg is
  quiet
• Use non-linear switching to control the output
  stage

14
Comparator Feedback with Dead-Band

• Use comparators in feedback path to generate
  full-swing drive signals
• To avoid limit cycle
• Offset thresholds to create dead-band

15
Output Stage Design

• Requirements on output stage
• Needs low td,on
• To maintain voltage- positioned response

• Needs good supply rejection
• Vshunt will be noisy
• Needs to burn minimal static power
• To meet efficiency goal

16
Replica Biased Output Stage

• Replica loop sets gate bias (Vbias)
• Minimal current spent in feedback amplifier for
  efficiency
• High impedance amp add buffer between Vbias and
  switching node

17
Switched Source Follower Buffer

• Source follower Mp_sf used to isolate Vbias
• Turned on only when pushing current
• But, waiting for Isf to charge Vgn too slow
• Mp_up turned on during transition

18
Outline

• Regulator Topology
• Regulator Design
• Experimental Verification
• Conclusions

19
Test-Chip Details

• 65nm SOI AMD test-chip
• Regulator uses same power distribution scheme as
  processor
• With reallocation for Vshunt
• On-chip noise generator and perf. monitor for
  testing

Processor
Regulator Circuits
Scan/Config.
20
Measured Results

• Regulator reduces broadband noise by 30
• Total power dissipation actually reduced by up to
  1.4

21
Impedance with Faster Process

• Process was in development
• Low device ft
• Measurement matches simulation with slower devices

• Expect to reach 50 noise and 4 power
  reduction in production process with higher ft

22
Outline

• Regulator Topology
• Regulator Design
• Experimental Verification
• Conclusions

23
Conclusions

• To be adopted, on-chip regulation must not
  increase total power
• Can in fact build power-neutral regulator
• Push-pull topology with second supply
• Switched source-follower output stage
• Measured 30 noise reduction with no power
  penalty
• In fact, reduced power by 1.4

24
Acknowledgements

• This work was funded in part by C2S2
  (www.c2s2.org)
• AMD Sunnyvale Design Center