APSR

1
APSR

• Matthew Bailes
• Swinburne University
• Of
• Technology

2
Baseband Pulsar Timing History

• Caltech Berkeley Processor
• 1996 10 MHz 2xDLT 7000
• Princeton Mk IV
• 1997 10 MHz 2xDLT 7000
• S2TCI (1997)
• York University/Melbourne Uni/Swinburne
• 16 MHz 8xVHS
• CPSR1 (1999)
• Caltech/Swinburne
• 4xDLT 7000

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Baseband History

• COBRA
• Coherent Baseband Recorder 2001?
• 150 Processors
• CPSR2 (2002)
• 2x64 MHz x 2bits x 2 pols
• 30 Xeon dual 2.3 GHz processors
• Arecibo Signal Processor (ASP) 03/04?
• 64 MHz with polyphase filters and 4 bits

4
Selected Achievements

• Princeton Mk IV
• MSP timing, 200 ns timing on 17130747
• PUMA2??
• Early results extremely promising
• CPSR1
• 130 ns timing on PSR J0437-4715
• CPSR2
• Polarimetry of 27 MSPs (Ord et al.)
• Giant Pulses discovered in MSPs (Thorsett et al.)
• Precision timing on 7 MSPs (lt 1 us) (Hotan et
  al.)
• 0437, 0613, 1600, 1713, 1744, 1909, 1937
• Several others near 1 us

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Giant Pulses
Giant Pulse (02184232)
2 microseconds wide!
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Timing
75 nanosecond timing
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Stability
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Profile Precision
Must be done with Coherent dedispersion
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Incoherent FB limitations

• 2048 channels/ 512 MHz
• L-band
• Terzan 5
• 190 us Smearing!
• Still need coherent dedispersion

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Current Generation
IF
Samplers FPGA
Bits
CPU RAM Buffer
CPU RAM Buffer
DMA
DMA
IF
Polyphase bits
Gb ethernet
Gb Switch
CPU
Gb Switch
CPU
CPU
CPU
CPU
CPU
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First ProblemFinite bandwidth.

• Largest baseband recorder is 1 Gb/second
• Nbits 2 x B x Pols x Nbits
• B 2x64 MHz
• Pols 2
• Nbits 2

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Second Problem2 bit distortions

• Imperfect sampling of input voltages

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(No Transcript)
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Channel 63/128
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Channel 31/128
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Channel 15/128
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Channel 123/128
Channel 7/128!
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Third ProblemFinite Computational Power

• At 20cm
• CPSR2 can do DMlt30 in real time!
• 56 Xeon 2.3 GHz processors
• Require
• 1 processor/3 MHz
• 512 MHz 170 processors
• 1024 MHz 340 processors

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Next Generation

• APSR
• ATNF/Parkes/Swinburne/Recorder
• 1-2 GigaByte/sec recorder/processor
• Much higher timing precision
• Nanosecond pulse sensitivity
• Lunar Experiments
• Giant pulses

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APSR
1 GHz x 2
IF
Samplers FPGA
10 Gb
Gb Switch
Polyphase bits
IF
Gb ethernet x16
16 Servers 128 CPUs
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Server Building Blocks

• Dual Quad-core 2.33 GHz servers
• 8x32bit Flops/core/cycle
• 149 32bit Gigaflops/server!
• 1 TB disk
• 2.3 32bit Teraflops
• Supercomputer total 21.6 32bit Teraflops!

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How much BW/How long?

• Benchmarks
• gt6 MHz/core (low DMs)
• gt3 MHz/core (high DMs)
• gt768 MHz (real time)
• 2 hour disk buffer/server but
• 128 MB/s exceeds disk IO rates!
• RAM can hold
• 2bit (256 seconds)
• 4bit (128 seconds)

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Inside Servers
16 GB RAM
Buffer
Buffer
Buffer
Buffer
128 MB/s
Disks
Buffer
Buffer
Buffer
CPUs
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Swinburne Supercomputer 2007(Green Machine)

• 1,160 x 2.33 GHz processing cores
• 10.811 64 bit Teraflops
• 2,320 GB RAM
• 145,000 GB disk (distributed)
• 126,000 GB disk (RAID)
• 72,000 GB DLT S4 robot
• (gt3 GHz for 6-station 1024 channels)

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Specs

• Limited to 128 MB/s (1 Gb/s) per host with
  channel bonding or 64 MB/s (512 Mb/s) without.
• (Current reasonable Gb to server limit)
• 16 Servers
• 64128 MB/s 16 Servers
• 24 bits x 64 MHz x 2 pols 1 GHz total
• 48 bits x 32 MHz x 2 pols 512 MHz total
• 88 bits x 16 MHz x 2 pols 256 MHz total

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Switch

• 48 ports
• 2 x 10 Gb ethernet
• 10 Gb uplink (bid into CISCO to get route to
  Swinburne Supercomputer)
• 10K?

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Required Modes

• Mode 1
• Raw data x 16
• 2/4/8 bits in clusters with time-tagging
• Mode 2
• Polyphase FB
• Set Nchan
• Set Nbit
• Set Nchannels/host

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Questions

• Can we get away without a FIFO?
• Will OS Glitches cause us to lose data?
• How will we know?
• Will it kill our observations?
• Is it better to coherently dedisperse 16 x 64 MHz
  bands or 1024 x 1 MHz????