Introduction to VLSI (ECE 349b)

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Introduction to VLSI(ECE 349b)
Wei Wang

• Electrical and Computer Engeering Dept.
• The University of Western Ontario
• London, ON, Canada
• Winter 2003

2

• Lecture 1
• Course Introduction
• Jan. 6 2003

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General

• 1. Welcome remark
• Definition of VLSI
• Importance of VLSI

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Course Requirement

1. Expectations
2. Academic industry
3. Rules
4. Attendance Assignment
5. Lab
6. Midterm final

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Information

• Text book in library
• Call no. TK7874.65.W65 2002
• Class notes and lab manual
• Ftp sun30.engga.uwo.ca
• Username ece480a
• Password ec.48.EC

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Information (contd)

• Labs
• 2 UNIX labs EC 2135 (Weeks of Feb. 4 and 18)
• Two PC labs EC1000 (Weeks of Mar. 4 and 18)
• (Tuesday, Wednesday and Thursday morning)
• Assignments
• Two weeks from the post date
• Drop-off box in front of lab

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Wei Wang

• Office EC 1006
• Office hours Monday and Wednesday
• 200 to 300 pm
• Email wwang_at_eng.uwo.ca

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Overview

• Why VLSI?
• Moores Law.
• ASIC Abstraction and Hierarchy.
• FPGA cheaper ASIC

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VLSI and you

• Microprocessors
• personal computers
• microcontrollers.
• DRAM/SRAM.
• Special-purpose processors.
• Many other applications telecom, DSP,etc.

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Moores Law

• Gordon Moore co-founder of Intel.
• Predicted that number of transistors per chip
  would grow exponentially (double every 18
  months).
• Exponential improvement in technology is a
  natural trend steam engines, dynamos,
  automobiles.

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Moores Law plot
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• Lecture 2
• Overview of VLSI
• Jan. 8 2003

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Overview

• Why VLSI?
• Moores Law.
• ASIC Abstraction and Hierarchy.
• FPGA cheaper ASIC

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ASIC and FPGA

• Application-specific integrated circuit design
• Field programmable gate array
• ASIC 2 UNIX labs (our main focus)
• FPGA 2 PC labs

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ASIC

• Top-down approaches

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Levels of abstraction

• Specification function, cost, etc.
• Architecture large blocks.
• Logic gates registers.
• Circuits transistor sizes for speed, power.
• Layout determines parasitics.

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Design abstractions
specification
behavior
register- transfer
logic
circuit
layout
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CAD Tools
specification
behavior
register- transfer
logic
circuit
layout
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ASIC Hierarchical name

• Interior view of a component
• components and wires that make it up.
• Exterior view of a component type
• body
• pins.

cout
Full adder
sum
a
b
cin
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ASICInstantiating component types

• Each instance has its own name
• add1 (type full adder)
• add2 (type full adder).
• Each instance is a separate copy of the type

cout
Add2(Full adder)
Add1(Full adder)
sum
sum
a
a
b
b
cin
cin
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Net lists and component lists

• Net list
• net1 top.in1 in1.in
• net2 i1.out xxx.B
• topin1 top.n1 xxx.xin1
• topin2 top.n2 xxx.xin2
• botin1 top.n3 xxx.xin3
• net3 xxx.out i2.in
• outnet i2.out top.out

• Component list
• top in1net1 n1topin1 n2topin2 n3topine
  outoutnet
• i1 innet1 outnet2
• xxx xin1topin1 xin2topin2 xin3botin1 Bnet2
  outnet3
• i2 innet3 outoutnet

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Component hierarchy
top
i1
xxx
i2
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Hierarchical names

• Typical hierarchical name
• top/i1.foo

component
pin
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Layout and its abstractions

• Layout for dynamic latch

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Stick diagram
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Transistor schematic
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Mixed schematic
inverter
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• Lecture 3
• Overview of VLSI (contd)
• Jan. 10 2003

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Overview

• Why VLSI?
• Moores Law.
• ASIC Abstraction and Hierarchy.
• FPGA cheaper ASIC

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Characteristics of ASIC

• Expensive
• Many cycles of design Simulation, synthesis
• Design for testing (DFT)

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Layout of ASIC
Pentium IV Technology 0.13 um Area 35
mm square Speed 2.2GHz Power 55 W
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Design abstractions
specification
behavior
register- transfer
logic
circuit
layout
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CAD Tools
specification
behavior
register- transfer
logic
circuit
layout
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Characteristics of FPGA

• Programmability
• Simulation, synthesis
• Test

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Layout of FPGA
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Top-down vs. bottom-up design

• Top-down design adds functional detail.
• Create lower levels of abstraction from upper
  levels.
• Bottom-up design creates abstractions from
  low-level behavior.
• Good design needs both top-down and bottom-up
  efforts.

39
Design abstractions
specification
behavior
register- transfer
logic
circuit
layout
40
CAD Tools
specification
behavior
register- transfer
logic
circuit
layout
41
Contents of the Course

• ASIC FPGA
• Transistor and Layout
• Gate and Schematic
• Systems and VHDL/Verilog

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Contents of the Course (contd)

• 2 ASIC labs 2 FPGA labs
• Transistor/Layout
• Gate and Schematic
• Systems/VHDL

(Cadence)
(Xilinx Foundation)
(Synopsys)
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The Future Is Not What It Used To Be
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Future of VLSI

• Nanotechnology
• Biotechnology
• Information technology

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