VLSI Arithmetic Adders

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VLSI ArithmeticAdders Multipliers

• Prof. Vojin G. Oklobdzija
• University of California
• http//www.ece.ucdavis.edu/acsel

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Introduction

• Digital Computer Arithmetic belongs to Computer
  Architecture, however, it is also an aspect of
  logic design
• The objective of Computer Arithmetic is to
  develop appropriate algorithms that are utilizing
  available hardware in the most efficient way.
• Ultimately, speed, power and chip area are the
  most often used measures, making a strong link
  between the algorithms and technology of
  implementation.

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Basic Operations

• Addition
• Multiplication
• Multiply-Add
• Division
• Evaluation of Functions

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Addition of Binary Numbers
Full Adder. The full adder is the fundamental
building block of most arithmetic circuits
  The sum and carry outputs are described
as
ai
bi
Full Adder
Cin
Cout
si
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Addition of Binary Numbers
Propagate
Generate
Propagate
Generate
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Full-Adder Implementation

• Full Adder operations is defined by equations

Carry-Propagate and Carry-Generate gi
One-bit adder could be implemented as shown
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High-Speed Addition
One-bit adder could be implemented more
efficiently because MUX is faster
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The Ripple-Carry Adder
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The Ripple-Carry Adder
From Rabaey
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Inversion Property
From Rabaey
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Minimize Critical Path by Reducing Inverting
Stages
From Rabaey
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Manchester Carry-Chain Realization of the Carry
Path

• Simple and very popular scheme for implementation
  of carry signal path

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Manchester Carry Chain

• Implement P with pass-transistors
• Implement G with pull-up, kill (delete) with
  pull-down
• Use dynamic logic to reduce the complexity and
  speed up

Kilburn, et al, IEE Proc, 1959.
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Ripple Carry Adder

• Carry-Chain of an RCA implemented using
  multiplexer from the standard cell library

Critical Path
Oklobdzija, ISCAS88
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Pass-Transistor Realization in DPL
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Carry-Skip Adder
MacSorley, Proc IRE 1/61 Lehman, Burla, IRE Trans
on Comp, 12/61
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Carry-Skip Adder
Bypass
From Rabaey
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Carry-Skip Adder N-bits, k-bits/group, rN/k
groups
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Carry-Skip Adder
k
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Variable Block Adder(Oklobdzija, Barnes IBM
1985)
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Carry-chain of a 32-bit Variable Block
Adder(Oklobdzija, Barnes IBM 1985)
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Carry-chain of a 32-bit Variable Block
Adder(Oklobdzija, Barnes IBM 1985)
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5
5
4
4
3
3
D9
2
2
1
1
Any-point-to-any-point delay 9 D as compared
to 12 D for CSKA
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Carry-chain block size determination for a 32-bit
Variable Block Adder(Oklobdzija, Barnes IBM
1985)
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Delay Calculation for Variable Block
Adder(Oklobdzija, Barnes IBM 1985)
Delay model
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Variable Block Adder(Oklobdzija, Barnes IBM
1985)
Variable Group Length
Oklobdzija, Barnes, Arith85
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Carry-chain of a 32-bit Variable Block
Adder(Oklobdzija, Barnes IBM 1985)
Variable Block Lengths

• No closed form solution for delay
• It is a dynamic programming problem

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Delay Comparison Variable Block
Adder(Oklobdzija, Barnes IBM 1985)
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Delay Comparison Variable Block Adder
VBA
CLA
VBA- Multi-Level
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Fan-Out Dependency
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Fan-In Dependency
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Delay Comparison Variable Block
Adder(Oklobdzija, Barnes IBM 1985)
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Carry-Lookahead Adder(Weinberger and Smith)
Weinberger and J. L. Smith, A Logic for
High-Speed Addition, National Bureau of
Standards, Circ. 591, p.3-12, 1958.
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Carry-Lookahead Adder(Weinberger and Smith)
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Carry-Lookahead Adder
One gate delay D to calculate p, g
   
One D to calculate P and two for G
Three gate delays To calculate C4(j1)
Compare that to 8 D in RCA !
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Carry-Lookahead Adder(Weinberger and Smith)
   
Additional two gate delays
C16 will take a total of 5D vs. 32D for RCA !
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32-bit Carry Lookahead Adder
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Carry-Lookahead Adder(Weinberger and Smith
original derivation )
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Carry-Lookahead Adder(Weinberger and Smith
original derivation )
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Carry-Lookahead Adder (Weinberger and
Smith)please notice the similarity with
Parallel-Prefix Adders !
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Carry-Lookahead Adder (Weinberger and
Smith)please notice the similarity with
Parallel-Prefix Adders !
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Delay Optimized CLA

• B. Lee, V. G. Oklobdzija
• Journal of VLSI Signal Processing, Vol.3, No.4,
  October 1991

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Delay Optimized CLA Lee-Oklobdzija 91
(a.) Fixed groups and levels (b.) variable-sized
groups, fixed levels (c.) variable-sized groups
and fixed levels (d.) variable-sized groups and
levels
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Two-Levels of Logic Implementation of the Carry
Block
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Two-Levels of Logic Implementation of the
Carry-Lookahead Block
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Three-Levels of Logic Implementation of the Carry
Block (restricted fan-in)
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Three-Levels of Logic Implementation of the Carry
Lookahead (restricted fan-in)
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Delay Optimized CLA Lee-Oklobdzija 91
Delay Three-level BCLA
Delay Two-level BCLA
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Delay Optimized CLA Lee-Oklobdzija 91
(a.) 2-level BCLA D8.5nS (b.) 3-level
BCLA D8.9nS
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Motorola CLA Implementation Example

• A. Naini, D. Bearden and W. Anderson, A 4.5nS
  96b CMOS Adder Design,
• Proceedings of the IEEE Custom Integrated
  Circuits Conference, May 3-6, 1992.

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Critical path in Motorola's 64-bit CLA
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Motorola's 64-bit CLAconventional PG Block
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Motorola's 64-bit CLAModified PG Block
Intermediate propagate signals Pi0 are
generated to speed-up C3
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Lings Adder

• Huey Ling, High-Speed Binary Adder
• IBM Journal of Research and Development, Vol.5,
  No.3, 1981.

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Ling Adder
Lings equations
Variation of CLA
Ling, IBM J. Res. Dev, 5/81
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Ling Adder
Lings equation
Propagates informationon two bits
Doran, Trans on Comp 9/88
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Ling Adder
Conventional
Ling
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S. Naffziger, ISSCC96
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S. Naffziger, ISSCC96
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S. Naffziger, ISSCC96
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S. Naffziger, ISSCC96
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S. Naffziger, ISSCC96
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S. Naffziger, ISSCC96
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S. Naffziger, ISSCC96
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S. Naffziger, ISSCC96
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S. Naffziger, ISSCC96
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S. Naffziger, ISSCC96
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S. Naffziger, ISSCC96
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ResultsS. Naffziger, A Subnanosecond 64-b
Adder, ISSCC 96

• 0.5u Technology
• Speed 0.930 nS
• Nominal process, 80C, V3.3V

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ConditionalSum Adder

• J. Sklansky, Conditional-Sum Addition Logic,
  IRE Transactions on Electronic
• Computers, EC-9, p.226-231, 1960.

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ConditionalSum Adder
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ConditionalSum Adder
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Carry-Select Adder

• O. J. Bedrij, Carry-Select Adder, IRE
  Transactions on Electronic Computers, June
• 1962, p.340-34

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Carry-Select Adder

• Addition under assumption of Cin0 and Cin 1.

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Carry Select Addercombining two 32-b VBAs in
select mode
Delay DVBA32 DMUX
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Addition Under Non-equal Signal Arrival Profile
Assumption

• P. Stelling , V. G. Oklobdzija, "Design
  Strategies for Optimal Hybrid Final Adders in a
  Parallel Multiplier", special issue on VLSI
  Arithmetic, Journal of VLSI Signal Processing,
  Kluwer Academic Publishers, Vol.14, No.3,
  December 1996

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Signal Arrival Profile form the Parallel
Multiplier Partial-Product Recuction Tree
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Oklobdzija, Villeger, IEEE Transactions on VLSI
Systems, June, 1995
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Oklobdzija and Villeger, IEEE Transactions on
VLSI Systems, June, 1995
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Performing Multiply-Add Operation in the Multiply
Time

• P. Stelling, V. G. Oklobdzija, " Achieving
  Multiply-Accumulate Operation in the Multiply
  Time", Thirteenth International Symposium on
  Computer Arithmetic, Pacific Grove, California,
  July 5 - 9, 1997.

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Final Adder Implementation
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Final Adder Implementation
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Final Adder Implementation
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Final Adder Implementation
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Recurrence Solver Based Adders

• Koggie and Stone, IEEE Trans on Computers, August
  1973
• Bilgory and Gajski, 18th DAC, 1981
• Brent and Kung, IEEE Trans on Computers, March
  1982

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Recurrence Solver Based Adders

• 1973, Koggie and Stone published a general
  recurrence scheme for parallel computation
• 1979, Brent and Kung published Tech. Report on
  regular layout for parallel adders
• 1980, Guibas and Vuillemin, developed a layout
  scheme based on recurrence equation for addition
• 1980, Ladner and Fisher published parallel
  prefix computation, Jo of ACM
• 1981, Bilgory and Gajski published a paper on
  recurrence structures for automatic cell
  generation

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Recurrence Solver Based Adders

• They are based on recurrence equation for P,G
• (what is new there since Weinberger ?!!)
• Or and

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Recurrence Solver Based Adders
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Carry-Lookahead Adder (Weinberger and Smith)Just
to remind you !please notice the similarity with
Parallel-Prefix Adders !
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Multiplexer Based Adder

• Farooqui and Oklobdzija
• 1999 Intl Sym. on VLSI Technology, Taipei,
  Taiwan, June 8-10, 1999

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Multiplexer Based Adder

• Based on the realization that MUX circuit is
  faster than a logic gate due to its transmission
  gate implementation
• Based on Carry-Lookahead method (W-S), or
  recurrence solver.

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Multiplexer Based AdderA. A. Farooqui, V. G.
Oklobdzija , F. Chechrazi, 1999 Intl Sym. on
VLSI Technology, Taipei, Taiwan, June 8-10, 1999.
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Multiplexer Based AdderA. A. Farooqui, V. G.
Oklobdzija , F. Chechrazi, 1999 Intl Sym. on
VLSI Technology, Taipei, Taiwan, June 8-10, 1999.
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Multiplexer Based AdderA. A. Farooqui, V. G.
Oklobdzija , F. Chechrazi, 1999 Intl Sym. on
VLSI Technology, Taipei, Taiwan, June 8-10, 1999.
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Multiplexer Based AdderA. A. Farooqui, V. G.
Oklobdzija , F. Chechrazi, 1999 Intl Sym. on
VLSI Technology, Taipei, Taiwan, June 8-10, 1999.

• Results in a very fast structure
• 7-MUX delays for a 64-b adder
• Delay using standard cell 0.25u, 2.5V, 25oC

Adder Size (bits) Delay (pS)
8 625
16 665
32 710
64 903
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DEC "Alpha" 21064 Adder

• Combination
• 8-bit tapered pre-discharged Manchester Carry
  Chains, with Cin 0 and Cin 1
• 32-bit LSB Carry Lookahead Adder
• 32-bit MSB Conditional-Sum Adder
• Carry-Select on most significant 32-bits
• Latches in the middle pipelined addition

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DEC "Alpha" 21064 Adder
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DEC "Alpha" 21064 Adder Results

• The first 200MHz processor
• Built using 0.75u technology
• V3.3V, 30W
• Pipelined (two-latches) allowing 5nS throughput
  and 10nS latency

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Conclusion

• VLSI Implementation of Addition

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Conclusion VLSI Implementation of Addition

• Currently, implementation parameters are not
  reflected in algorithms used for development
• Layout and wire delays effects are largely
  neglected and this is becoming intolerable in the
  next generation of technology
• Transistor sizing has a large effect which can
  outweight the algorithm
• There is a great disconnect between algorithm and
  implementation
• New rules and measures of goodness are needed

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Multiplication

• Parallel Multiplier Implementation

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Multiplication

• Algorithm

initially
for j0,....,n-1
p(n)XY after n steps
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Parallel Multipliers

• Parallel Multipliers

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42 Compressor
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Re-designed 42 Compressor with 3 XOR Delay
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Three-Dimensional optimization Method
TDM(Oklobdzija, Villeger, Liu, 1996)
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Generation of the Partial Product Reduction Tree
in TDM multiplier
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Speed of Partial Product Reduction for Various
Schemes
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Booth Recoding Algorithm
xi2xi1xi Add to partial product
000 0Y
001 1Y
010 1Y
011 2Y
100 -2Y
101 -1Y
110 -1Y
111 -0Y
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Organization of Hitachi's DPL multiplier
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Hitachi's 42 compressor structure
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DPL multiplexer circuit
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Conclusion

• References
• E. Swartzlander, "Computer Arithmetic". Vol. 12,
  IEEE Computer Society Press, 1990.
• K. Hwang, "Computer Arithmetic Principles,
  Architecture and Design", John Wiley and Sons,
  1979.
• M. Ercegovac, Digital Systems and
  Hardware/Firmware Algorithms, Chapter 12
  Arithmetic Algorithms and Processors, John Wiley
  Sons, 1985.
• A. Chandrakasan, W. Bowhill, F Fox, Editors,
  "Design of High Performance Microprocessors
  Circuits", IEEE Press, July 2000.
• V. G. Oklobdzija, High-Performance System
  Design Circuits and Logic, IEEE Press, July
  1999.
• Also http//www.ece.ucdavis.edu/acsel/Publicatio
  ns.html