RF FrontEnd for MCMA Systems

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RF Front-End for MCMA Systems

• D. Cabric1, H.-M. Bluethgen2, and Prof. R. W.
  Brodersen11University of California, Berkeley,
  2Infineon Technologies, Munich

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Objective

• Design RF front end compatible with the BEE
  platform for Multi-Carrier Multi-Antenna (MCMA)
  systems
• Specify front-ends architecture and components
• Provide flexibility to append further up/down
  conversion stages (e.g. 24 GHz and 60 GHz)

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Design Considerations

• Each antenna RF chain requires
• Dual DAC board, dual ADC board, antenna, control
  signals, power supply
• Interface with the BEE board
• Clean clock sources for ADC and DAC
• I/Q channel data buses
• RF gain control for the AGC
• Phase noise of sample clocks
• How are different sample clock phases affecting
  the system?
• What is the tolerance in the misalignment of
  transmitted symbols?
• Same problem applies to the receiver sampling
• Phase noise of IF and RF signals
• Can we use seperate PLLs for all channels?
• Alternatively, we can use a common carrier signal
  produced externally(IF/RF signal generator)

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Optimal Architecture

• All RF transceivers for multi-antenna system
  integrated on one board
• All up-/down-conversion mixers fed by common
  reference signals

• Common phase noise on each antenna branch
• Good matching of all components and signals on
  the board
• Less components
• Compact, easier to calibrate and handle
• Fixed number of antennas
• Requires dedicated PCB design

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Alternative Architecture

• One separate board for each antenna
• One PLL on each board

• Single LO to generate IF and RF frequencies
• Arbitrary number of antennas
• Flexible and reusable
• Commercial front-ends available
• Need to program each PLL individually
• After PLL phase noise is different on each
  antenna

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Available Single-Antenna Front-End Reference
Designs
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FPGA Implementation of a Narrow-Band
Transmission System
Transmitter
Simulink Model of Transmission System
Receiver
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Implementation onPicoNode 2 Board
Channel
Receiver
Transmitter
Tx I
Rx I
Out1
I
I
Out2
Q
Q
Ctrl
Ctrl
Tx Q
Rx Q
Simulink Model
System Generator
System Generator
BEE Design Flow
BEE Design Flow
BitstreamFile
BitstreamFile
FPGA
FPGA
FPGA
RF Front-End
ADC/DAC
PN2 Board 1
PN2 Board 2
M. Kuulusa, PicoNode 2 Prototype, BWRC Summer
Retreat 2002
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Measurements
Tx Output Spectrum
Eye Diagram
Constellation Diagram
RF Front-EndA/D Conv.
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Outlook

• Determine and characterize all contributing noise
  sources
• Quantitative comparison of architecture
  alternatives
• Derive a model for simulations from measurements
• Use simulation model to extend single-antenna
  results to multi-antenna system
• Consideration of different multi-element antenna
  configurations
• Specification for RF front-end
• Implementation of parallel multi-antenna front-end