HW/SW Interface

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HW/SW Interface

• Operating Systems Design and Implementation

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Foreground/Background Systems

• Often referred to as super-loops

Infinite loop calling modules
ISR
Handle Asynchronous Events
ISR
ISR
Interruption occurred
Foreground (interrupt level)
Background (task level)
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Interrupt Service Routines

• Handle critical operations
• can take longer than they should
• make data available for background routines
• processing of such information is referred to
  task-level response

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Example EFI System(Electronic Fuel Injection)

• What are the components?

Throttle Body
Cold start solenoid
Air-flow meter
Injectors
O2 sensor
ECU
Water temperature sensor
Distributor sensors
High pressure fuel pump
manifold sensor
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EFI System

• How does it work?
• fundamentally, it manages three necessities to
  start and maintain operation of a gasoline engine
• fuel
• spark
• air

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EFI System

• What happen to the EFI system when you start a
  car?
• What happen to the EFI system when you drive a
  car?

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Dissecting EFI System

• Tasks

• ISRs

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EFI System

• Critical section (atomic or indivisible)
• any possible critical regions in our tasks?
• Mutual exclusion?
• Reentrant code?
• functions can be used by multiple tasks without
  causing data corruption
• Priority inversion problem?

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Priority Inversion

• Assume task 3 has lower priority than task 1.
• Task 1 is doing I/O so Task 3 gets to run
• Task 3 is in the middle of accessing a shared
  resource (obtain semaphore)
• Task 1 finishes so it preempts Task 3
• Task 1 wants to access the same resource but
  cant since Task 3 has the semaphore

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Priority Inversion

• In this scenario, the priority of Task 1 is
  reduced to that of Task 3.
• What is a good solution?

Priority Inheritance
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Priority Inversion

• Priority Inheritance
• Task 1 is doing I/O so Task 3 gets to run
• Task 3 is in the middle of accessing a shared
  resource (obtain semaphore)
• Task 1 finishes so it preempts Task 3
• Task 1 wants to access the same resource but
  cant since Task 3 has the semaphore thus the
  kernel raises the priority of Task 3 to the same
  as Task 1
• Task 3 gets to finish and releases the resource.
  The priority is reset to the original value
• Task 1 is selected if it still has the highest
  priority

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Assigning Task Priority

• Rate monotonic scheduling
• tasks with the highest rate of execution are
  given the highest priority
• Assume all tasks are periodic
• Tasks do not synchronize with another, share
  resources, and exchange data
• Preemptive scheduling is used

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Assigning Task Priority
Number of Tasks n(21/n - 1)
1 1
2 0.82
3 0.77
4 0.75
5 0.74

- 0.69
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Providing Mutual Exclusion

• Disabling interrupt
• Test and Set operation
• hardware support (TSL operation)
• Disabling scheduler
• Semaphores
• how is semaphore implemented?

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Disabling Interrupt

• X86
• CLI (disable interrupt)
• STI (enable interrupt)

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Busy Waiting
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Busy Waiting
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Semaphore

• Is a type that has a counter and a delay queue
• require OS support as processes in the delay
  queue are blocked
• implementation often requires other primitive
  support (disabling interrupt, etc.)

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Semaphore
assumes the existence of binary semaphore
operations upb and downb implemented with a
test-and-set instruction and busy waiting
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Intertask Communication

• Message mailbox
• Message queues
• often use to process interrupt

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Interrupts

• A hardware mechanism used to notify the CPU that
  asynchronous events have occurred
• Upon completion, the programs return to
• background for a foreground/background system
• the interrupted task for non-premptive kernel
• the higest priority task ready to run for
  premptive kernel

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Example Interrupt in NIOS
IE bit to enabling interrupt IPRI bits for
priority MISC bits for interrupt control
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Source of Exceptions (NIOS)

• External Hardware interrupt Sources
• External logic for producing the 6-bits
  interruptnumber asserting the IRQ input pin is
  automatically generated by the SOPC builder and
  is included in the Peripheral Bus Module (PBM).
• Internal Exception Sources
• 2 sources of internal exceptions
• Register window-overflow, Register
  window-underflow
• Direct Software Exceptions
• Software can request that control be transferred
  to an exception handler by issuing a TRAP
  instruction.

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External Hardware Interrupts

• Active-high interrupt signal irq
• Level sensitive
• Sampled synchronously at the rising edge of Nios
  clock
• Should stay asserted until the interrupt is
  acknowledged by software
• 6-bit Input Interrupt Number irq_number50
• Identifies the highest priority interrupt
  currently requested
• Highest priority 0 (irq 0 to 15 are
  reserved)
• Lowest priority 63

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External Hardware Interrupts

• Nios will process the indicated exception if
• IE 1 i.e. external interrupts internal
  exceptions are enabled, AND
• The interrupt number is smaller (lower or equal)
  than the IPRI field value

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Internal Hardware Interrupts
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Interrupt Service Routine Handler

• nr_installuserisr( int trapNumber, void
  ISRProcedure, int context)
• trapNumber is the exception number to be
  associated with a service routine
• ISRProcedure is a routine which has a prototype
  of typedef void (Nios_isrhandlerproc) (int
  context)
• context is a value that will be passed to the
  routine specified by isrProcedure

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ISR Handler

• This routine installs an interrupt service
  routine for a specific exception number
• If nr_installuserisr() is used to set up the
  exception handler, then the exception handler can
  be an ordinary C routine

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ISR Process
Memory
Main Program
Save Context

• Interrupt occurs
• Current state is saved (Context)
• ISR address is retrieved from the vector table
  based on the interrupt number
• Jump to ISR routine
• Runs to completion
• Context is restored
• Program resumes

Restore Context
ISR
Vector Table
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ISR Implementation
Specify your IRQ
Declare your IRQ subroutines
Update the ISR vector table
Write your IRQ Subroutine
Write your IRQ Subroutine
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Interrupt Example

• UART (Universal Asynchronous Receiver
  Transmitter)
• Transferring data between processor and I/O
  devices
• Handle one 8-bit data at a time
• Transfer in parallel between UART and Processor
  and in bit-serial between I/O device and UART

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JTAG UART
Used to provide a connection between a Nios II
processor and the host computer connected to
the DE 2 board
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JTAG UART

• Data and control registers accessed by Nios II as
  memory locations

of char remaining in the read FIFO
read/write data from FIFOs
read valid
read/write interrupt enable
read/write/JTAG pending
available space in write FIFO
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JTAG UART
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JTAG UART

• Polling vs. Interrupt