3 Combinational Logic Design 31 Combinational Circuits

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3 Combinational Logic Design 3-1 Combinational
Circuits

• Combinational Circuits and Sequential Circuits
• Combinational Circuits
• consists of input variables, out variables, logic
  gates
• performs an operation that be specified logically
  by Boolean expressions

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3-2 Design Topics

• For effective and efficient digital design
• computer aided design tools
• hardware description languages(HDL)
• logic synthesis
• design hierarchy
• top-down design
• Design hierarchy
• divide and conquer (Fig 3.2)
• blocks (Fig 3.2(b),(c),(d))
• logic diagram or schematic (Fig 3.2(b) for (a))
• 1. Reduces the complexity
• 2. Ends at the set of leaves (primitive blocks)
• primitive blocks are a rudimentary type of
  predefined blocks (XOR)
• 3. Reuse of blocks (instance of the block) (Fig
  3.3)

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Top-Down Design and CAD

• top-down design
• Ideally, the design will be performed top down.
• Bottom up design
• For reusability and maximum use of predefined
  modules
• Computer Aided Design (CAD)
• Schematic capture tools support the drawing of
  blocks and interconnections
• At the level of primitives and functional blocks,
  libraries of graphics symbols are provided.

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HDL and Logic Synthesis

• hardware description language(HDL)
• describing hardware structures and behavior
• providing an alternative to schematics
• providing a more uniform, portable representation
  for simulation input.
• VHDL (VHSIC Hardware Description Language)
• VHSIC (Very-High Speed integrated circuits)
• Verilog HDL(1983, Gateway Design Automation)
• Logic Synthesis(Fig. 3.4)

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3-3 Analysis Procedure

• Analysis for a combinational circuit
• Determining the function that the circuit
  implements
• Make sure that the given circuit is combinational
• Obtain the output Boolean functions or the truth
  table
• Derivation of Boolean functions (Fig. 3.5)
• 1. Label all gate output
• 2. Label the gates that are a function of input
  variables and previously labeled gates
• 3. Repeat step 2 until the outputs are obtained
  in terms of the input variables

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Derivation of Truth Table

• Derivation of Truth Table
• 1. Determine the number of input variables
• 2. Break the circuit into small single-output
  blocks by labeling each block output with an
  arbitrary symbol
• 3. Obtain the truth table for blocks with
  functions that depend on input variables only
• 4. Proceed to obtain the truth table for blocks
  with functions that depend on previously defined
  inputs and block output

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Logic Simulation

• Fast and accurate method of analyzing a
  combinational circuit
• Net list
• specifies using text, the inputs, gates, outputs,
  and their interconnections or HDL description
• also be a logic schematic
• schematic capture tool
• provides a wiring tool that permits the gates to
  be interconnected and a labeling tool to label
  the schematic
• provides a tool for generating symbols that can
  be used in the schematic to procedure a design
  hierarchy

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