Hybridthreads Compiler: C to VHDL Jim Stevens (jstevens@ittc.ku.edu) and Fabrice Baijot (bricefab@ittc.ku.edu) - PowerPoint PPT Presentation

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Hybridthreads Compiler: C to VHDL Jim Stevens (jstevens@ittc.ku.edu) and Fabrice Baijot (bricefab@ittc.ku.edu)

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Allow for fast design space exploration. Enable software engineers to create custom hardware ... code that implements the hardware thread with a finite state ... – PowerPoint PPT presentation

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Title: Hybridthreads Compiler: C to VHDL Jim Stevens (jstevens@ittc.ku.edu) and Fabrice Baijot (bricefab@ittc.ku.edu)


1
Hybridthreads Compiler C to VHDLJim Stevens
(jstevens_at_ittc.ku.edu) and Fabrice Baijot
(bricefab_at_ittc.ku.edu)
Background
Approach
  • Leverage existing GCC front end with custom VHDL
    back end
  • HIFGEN extension to GCC translates GIMPLE into
    new Hardware Intermediate Form (HIF) language
  • Back end is a compiler for HIF called HIF2VHDL
  • Hthreads OS eliminates the HW/SW boundary for
    CPU/FPGA applications
  • Threads in both software and hardware
  • OS services available to hardware threads
  • Creating hardware threads in VHDL still difficult
    for software engineers
  • Need a compiler that can translate unaltered C
    threads into VHDL
  • Allow for fast design space exploration
  • Enable software engineers to create custom
    hardware

Design Flow
Implementation
Status
  • HIFGEN
  • Walks GIMPLE tree to generate equivalent HIF
  • Runs after GCCs GIMPLE optimizers (many free
    optimizations)
  • HIF2VHDL
  • Parses and type checks the HIF code
  • Elaborates HIF into a low level CFG language
  • Clean up optimizations
  • Generates VHDL code that implements the hardware
    thread with a finite state machine
  • HTC 1.0 (completed summer 2006)
  • 32-bit primitive types/operations (ints and
    pointers)
  • Aggregate types/operations (arrays and structs)
  • Demonstrates function call model in hardware
    threads
  • HTC 2.0 (currently in development)
  • Complete support for ANSI C language
  • Framework for future research in high-level
    language to hardware compilation and FPGA
    programming models
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