DESIGNING DIGITAL ASICS

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DESIGNING DIGITAL ASICS

• ECE 551
• FALL 2001
• Don Bouldin, Ph.D., P.E.
• Prof. of Electrical Computer Engineering
• University of Tennessee
• TEL [phone]
• FAX [phone]
• dbouldin_at_utk.edu

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COURSE OUTLINE

• Product Development Flow
• Technology-Independent Design
• Using Hardware Description Languages
• VHDL and Verilog Syntax

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A VARIETY OF ASICS ARE POSSIBLE
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APPLICATIONS MAY USE STANDARD ICs or FPGAs/ASICs
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THE COST PER GATE DECREASES AS THE DENSITY OF AN
I.C. INCREASES

• Microprocessors and other off-the-shelf LSI/VLSI
  chips are the most cost-effective because
  thousands of gates are available in a single
  chip. (0.001/gate 2000 gates/pin)
• SSI/MSI glue logic chips are the least
  cost-effective because only a few gates are
  available in a single chip. (0.01/gate 1-3
  gates/pin)

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SYSTEM FUNCTIONS ARE OFTEN SPLITBETWEEN THE
MICROPROCESSOR AND AN ASIC

• The most economical means of implementing logic
  functions is to use a microprocessor.
• When the microprocessor is too slow or too busy
  to handle some fast inputs and outputs, an ASIC
  can be used to implement "random" logic.

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PROGRAMMABLE LOGIC DEVICES AREBEST FOR SIMPLE
DESIGNS WITH MANY INPUTS OUTPUTS
PLDs

• Vendor prefabricates multiple sets of ANDs and
  ORs with programmable connections
• User specifies connections to implement desired
  logic functions
• Replaces 300 to 8000 gates with single package of
  20-84 pins
• Electrically programmable (and erasable) by the
  user one at a time within minutes
• PC-based development system costs 3-5K

and
and
or
and
and
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MASK GATE ARRAYS ARE BEST FOR MODERATE-SIZED
DESIGNS THAT ARE TIME-TO-MARKET CRITICAL

• Vendor prefabricates rows of gates and stockpiles
  wafers
• User specifies two layers to implement logic
  functions
• Replaces 10,000 to 10,000,000 gates (or more)
• After place route, masks are made for two
  layers
• Workstation-based development system costs 50K
• Turnaround time for prototypes is 3-5 weeks

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FIELD-PROGRAMMABLE GATE ARRAYS ARE BEST FOR
LOW-QUANTITY APPLICATIONS

• Vendor prefabricates parts with rows of gates and
  programmable connections
• User specifies connections to implement logic
  functions
• Replaces 2,000 to 2,000,000 gates (or more)
• Electrically programmable (some are erasable) by
  the user one at a time within hours
• Production quantity lt 20,000
• PC-based development system costs 5-10K

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STANDARD LIBRARY CELLS ARE BEST FOR HIGH-QUANTITY
APPLICATIONS WITH SIGNIFICANT FUNCTIONS
(MULTIPLIERS, CPU, RAM, ETC.)

• Vendor develops library disk files of significant
  functions
• User selects cells and specifies two layers of
  interconnections
• After place route, masks are made for all
  layers
• Replaces 100,000 to 10,000,000 gates (or more)
• Workstation-based development system costs 100K
• Turnaround time for prototypes is 8 weeks

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BIT-SLICE DATA PATHS ARE BEST FOR
SPECIAL-PURPOSEPARALLEL PROCESSING

• User develops bit-slices to be replicated
• Most efficient use of silicon
• Masks are made for all layers
• Replaces 100,000 to 10,000,000 gates (or more)
• Workstation-based development system costs 150K
• Turnaround time for prototypes is 8 weeks

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ALTERA FLEX-10K FPGA LAYOUT
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DETAILED LAYOUT OF XILINX FPGA
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A MASK GATE ARRAY CAN BE STOCKPILED AND THEN
PERSONALIZED

• The fabricator provides basic gates with space
  for interconnect.
• The application designer submits a logic net-list
  which defines the interconnect layers.

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A MASK GATE ARRAY MAY CONTAINEMBEDDED RAM
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STANDARD-HEIGHT CELL DESIGNSREQUIRE ALL MASKS
FOR FABRICATION

• Only logic cells which are needed are fabricated.
• Higher performance and less area can be achieved
  but fabrication takes longer.

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STANDARD-HEIGHT CELL CHIPS CANALSO USE EMBEDDED
RAM
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DATAPATH OR BIT-SLICE LAYOUTIS THE MOST EFFICIENT
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BEE-TRACKING APPLICATION
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FPGAS COVER HIGH-END PROGRAMMABLE LOGIC DEVICE
APPLICATIONS AND LOW-END MASK GATE ARRAY
APPLICATIONS
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RECONFIGURABLE vs. HARDWIRED FPGA
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MINIMIZING AREA INCREASES BOTH THE NUMBEROF
POTENTIAL SITES AND YIELD
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XILINX HIGH VOLUME APPLICATIONS
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APPLICATIONS OF FPGAS

• TTL/PLD Replacement
• MGA Prototyping
• Distributed Arithmetic for DSP
• Diagnostics/Testing of Other Ics
• Communication Protocol Controller
• Monitor (Portrait/Landscape)
• Position Tracker for Robot Manipulator
• Flexible Co-Processor

• CCD Imaging System Controller
• Printer Controller
• Tape Drive Controller
• Fast DMA Controller
• Artificial Neural Networks
• Hardware Accelerator

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FPGAs versus MGAs
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ASIC MARKET BREAKDOWN
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TOP TEN SEMICONDUCTOR COMPANIESIN BILLIONS OF
DOLLARS OF CAPITAL
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MICROELECTRONIC SYSTEM DESIGNCONSISTS OF
ITERATIVE REFINEMENTSOF SYNTHESIS AND
VERIFICATION
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SYNTHESIS AND PLACE ROUTE SOFTWARE CANBE USED
TO GENERATE THE IMPLEMENTATION
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ASIC DESIGN BREAKDOWN
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SYNTHESIS AND PLACE ROUTE SOFTWARE CANBE USED
TO GENERATE THE IMPLEMENTATIONS
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ASIC DESIGN FLOW
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PROFIT MODEL SHOWING VALUEOF TIME-TO-MARKET
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FIXED COSTS FOR FPGAS/ASICS
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VARIABLE COSTS FOR FPGAS/ASICS
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BREAK-EVEN ANALYSIS FOR FPGAS/ASICS
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DESIGN FLOW FOR FPGAS AND ASICS
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COMPARISON OF PRODUCT DEVELOPMENT
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COMPARISON OF PRODUCT COSTS
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SYNTHESIS AND FPGAS CAN REDUCETIME-TO-MARKET

• Synthesis can reduce the design time required to
  achieve and verify a given functionality since
  many candidate solutions can be constructed
  quickly and accurately.
• Simulation is required for verification and risk
  reduction but is time-consuming and may not be
  entirely representative of the full system
  environment.
• Prototyping with FPGAs can speed verification and
  reduce risk.

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REDUCTION IN TIME-TO-MARKETINCREASES PROFITS
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DESIGN AT THE BEHAVIORAL LEVEL USING A HARDWARE
DESCRIPTION LANGUAGE AND SYNTHESIS

• The desired functionality and timing may be
  described using a hardware description language
  such as VHDL or Verilog and then synthesized into
  the structural level for a specified technology.
• Synthesis involves
• (1) translation into Boolean
  equations,
• (2) optimization of these for area or
  delay, and then
• (3) mapping to a semicustom technology
  (library).
• The physical level is then implemented
  automatically using a placement and routing
  program.

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APPROPRIATE USE OF HDL AND SCHEMATICS

• Design capture is facilitated when it is a
  straightforward transcription of what the
  designer has in mind.
• Controller behavior can best be captured with a
  HDL (hardware description language) using
  primarily if-then-else statements.
• Structure which defines the interconnections
  among components can best be captured graphically
  using schematics but a HDL can also be used.
• HDL and schematics can be mixed for the best of
  both worlds.

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USING SYNTHESIS WISELY

• Synthesis can provide an improvement in designer
  productivity by trading CPU cycles for human
  sweat. Designers can use synthesis to achieve a
  higher quality solution in less time.
• Synthesis facilitates retargeting a design from
  one FPGA technology to another or to Mask Gate
  Arrays when the requirements are frozen and the
  production quantity is sufficient.
• Synthesis is not a panacea since it presently
  produces larger and slower solutions than
  experienced designers. Direct targeting to FPGAs
  is helping.

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TECHNOLOGY-INDEPENDENT DESIGN SHOULD BE PRACTICED
AS MUCH AS POSSIBLE

• Most of a design can be specified without
  referring to details of the technology.
• This technology-independence permits the design
  to be captured once and then synthesized into
  multiple technologies over a period of time.
• Thus, the selection of an IC foundry can be made
  on a competitive basis or changed as new
  processes become available each year.

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PRINCIPLES OF SYSTEM OPTIMIZATION

• A global figure of merit for the entire system
  should be determined and optimized
• This figure of merit involves multiple dimensions
  including cost, area, speed, power, design time,
  risk, etc.
• Optimization of a particular level or component
  of a system may not constitute a good return on
  investment.
• Decisions made at the higher levels of the design
  are often more significant than at the lower
  levels.
• Designers should pinpoint and concentrate on
  sensitive components for which small changes
  yield big payoffs.

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THE ORIGINAL AND PRESENT USES OF VHDL

• VHDL VHSIC HDL Very High-Speed Integrated
  Circuit Hardware Description Language
• In 1981 VHDL was developed by the US Dept. of
  Defense to standardize documentation for
  maintenance or possible redesign.
• In 1987 IEEE approved a VHDL standard.
• Since then, CAE companies have been using VHDL
  with enhancements for synthesis.
• In 1992, a new IEEE standard with many of these
  synthesis enhancements was approved.

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VERILOG

• VERILOG is a hardware description language
  originally developed by Gateway Automation
  (Cadence) for verification of logic.
• Cadence and other CAE companies have been using
  Verilog with enhancements for synthesis.
• Most users say Verilog is easier to learn than
  VHDL.
• VERILOG is no longer proprietary.
• A VERILOG users' group broadcasts newsletters.

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TRUTH TABLE OR EQUATIONS USING VHDL
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IEEE STD_LOGIC_1164 PACKAGE
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MUX USING IF-THEN-ELSE IN VHDL
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DEC2TO4 USING CASE IN VHDL
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BCD-TO-7SEG CONVERTER USING VHDL
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BINARY UP-COUNTER USING VHDL
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TWO-DIGIT BCD COUNTER
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STATE DIAGRAM AND STATE TABLEWITH BINARY
ASSIGNMENT
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LOGIC MINIMIZATION USING K-MAPS
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LOGIC EQUATIONS AND SCHEMATIC
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STATE DIAGRAM AND FINAL SCHEMATIC
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ALGORITHMIC STATE MACHINE(ASM) FLOW CHART
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ASM CHART IN VHDL (part 1)
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ASM CHART IN VHDL (part 2)
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ASM CHART IN VHDL (part 3)
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ASM CHART IN VHDL USING ONE PROCESS
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A SCHEMATIC CAN SPECIFY STRUCTURE WITH
COMPONENTS AND INTERCONNECTIONS
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VHDL CAN SPECIFY STRUCTURE (part1)
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VHDL CAN SPECIFY STRUCTURE (part2)
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VHDL CAN SPECIFY STRUCTURE (part 3)
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STRUCTURAL HIERARCHY
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MENTOR GRAPHICS DESIGN MANAGERAND DESIGN
ARCHITECT
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MENTOR GRAPHICS SCHEMATIC