Memory Management A companion to the handout

1
Memory Management(A companion to the handout)
UNIVERSITY of WISCONSIN-MADISONComputer Sciences
Department
CS 537Introduction to Operating Systems
Andrea C. Arpaci-DusseauRemzi H.
Arpaci-Dusseau Haryadi S. Gunawi

• Dynamic relocation (base and bounds)
• Segmentation
• Paging
• Segmentation Paging

2
Dynamic Relocation

• A) Whats the OS job to create P1?
• Assign 1 MB for the bounds for P1
• Allocate 1 MB physical address at addr 2000
  (which become the base)
• Create P1s PCB and put the base (2000) and
  bounds (1MB) in the PCB
• Load the base and bounds to the MMU
• B) What happens if P1s memory grows larger than
  1 MB?
• If the neighboring physical address is empty, we
  just increase the bounds
• But if not, we must relocate all P1s memory
  (change the base address and assign a new larger
  bounds)
• C) What happens on context switch to P2?
• Base and bounds in the MMU must be reloaded with
  P2s base and bounds
• And more other stuffs we talked in the last
  lecture

3
Dynamic Relocation

• 1) Easy relocation (just change the base)
• -1) External fragmentation
• Ex if a big process comes in and no hole that
  could fit the process, we must defragment the
  memory (time consuming! All processes must
  freeze)
• -2) Sharing?
• Code sharing is impossible
• -3) Internal fragmentation
• A small process but is given large memory
• -4) Hard to grow
• Ex A small process grows to a big process
• If neighboring addresses are not empty, we must
  relocate the whole memory of the process

4
Segmentation

• A) OS job when P1 is created?
• Create a segment table for P1 in the memory
• For each segment
• Assign and store bounds (e.g. stack 3 MB, heap 2
  MB, code 1 MB)
• Allocate memory (as big as the specified bounds),
  and store the address (e.g. stack at 9000, heap
  at 8000, code at 2000)
• Create P1s PCB and stores the segment in the PCB
• Load the segment table of P1 into the MMU
• Segment table is small, so it can fit in the MMU
  hardware
• B) If P1s heap grows?
• If neighboring addresses are empty, just increase
  the bounds of P1s heap segment
• Else, must relocate only P1s heap segment
  (change P1s heap base and bounds). Code and
  stack segments stay in the same place.
• C) Context switch from P1 to P2?
• Reload the MMU with P2s segment table
• And other details

5
Segmentation

• 1) Segment independently grows and relocated
• If heap grows and is relocated, stack and code
  stay put
• 2) Sharing
• Can easily share a segment (e.g. code segment)
• How to do that? Just share the base and bounds of
  the segment (i.e. base and bounds of P1s and
  P2s code segment are the same)
• -1) External fragmentation
• Still, a segment could be big
• If no hole fits, we must relocate the segment
• Why? Because the segment must reside in
  contiguous address
• How to make a segment not to reside in contiguous
  address? ? Answer Paging

6
Paging

• Goal Eliminate external fragmentation
• Idea Divide memory into fixed-sized pages
• Size 2n, Example 4KB (n 12)
• Physical memory is composed of page frames
• Addressing (how to translate virtual address to
  physical address?)
• High-order bits of virtual address designate page
  number (or sometimes called virtual page number)
• Low-order bits of address designate offset within
  page (i.e. page offset)
• The page table converts page number to frame
  number (or sometimes called physical page
  number).
• 1 Page table per process
• Each process knows the base address of its page
  table (PT Base)
• The entry in the page table is called Page Table
  Entry (PTE)
• A PTE contains the frame number and R/W
  protection bits

7
Paging

• Q1) Page size?
• Depends. Use 12 bits for page offset, page size
  is 4 KB
• Q2) of entries in the page table?
• In 32-bit architecture, we use 20 bits (32 12)
  for the page number. The page number is used to
  index the page table.
• Hence, 220 entries
• Q3) Page table size?
• PT size entries width of a PTE
• Width of a PTE 20 bits frame number R/W bits
  22 bits (But lets just say 32 bits (or 4
  bytes) for simplicity and word alignment)
• PT size 2 20 4 Bytes 2 22 bytes 4
  MB (for each process!)
• Q4) Does a page table can be reloaded to MMU?
• No! too big!
• Q5) So, how to find the page table of a process?
• The PCB of that process stores the PT Base

8
Paging

• A) What happens after system boot?
• OS gets its memory in the top-part of the memory
• This memory is used to store PCBs, page tables,
  etc.
• B) Job of OS to create P1 with 8 KB code?
• Create a page table (4MB) in the memory
• Stores the PT Base address to P1s PCB
• Allocate and point to physical frames
• First, P1 could access page 0 and 1
• Allocate 2 physical frames for page 0 and 1
  (dont have to be contiguous, say frame 1, and
  frame 4)
• Assign PT0 1 and PT1 4
• Load only the P1s PT Base Address to the MMU
• C) Addressing when a process runs? Next slide
• D) malloc(1Byte)
• Almost the same as part (B) above. Try it
  yourself.
• E) malloc many times
• OS allocate as many physical frames as needed
• Update the page table appropriately, e.g. PT
  3456 8009
• 3456 is page number, 8009 is frame number
• Return virtual address to the malloc() caller

9
Paging

• 1) No external fragmentation
• Any page can be placed in any frame in physical
  memory
• Simple linked-list free space management
• Fast to allocate and free
• Alloc No searching for suitable free space,
  simply take the head
• Free Doesnt have to coalesce with adjacent free
  space
• 2) Simple free space management
• E.g. Free bits, or linked list of free frames
• To get a new frame, just take the head of the
  list
• 3) Fine-grained sharing
• To share a page, have PTE point to same frame
• The OS could create a frame for two processes to
  share (i.e. there are two PTEs pointing to the
  same frame)
• 4) Easy to swap out (more next week)
• Page size matches disk block size
• Can run process when some pages are on disk
• Add present bit to PTE

10
Paging

• -1) Best page size?
• Too big? Internal fragmentation
• Too small? Huge page table!
• -2) Huge page table
• Simple page table Requires PTE for all pages in
  address space
• Entry needed even if page is not allocated
• Most likely because a processs view of memory
  virtual address space for all three segments
  (code, stack, and heap)
• -3) Inefficient
• Additional memory reference to look up in page
  table
• Page table must be stored in memory
• MMU stores only base address of page table
• 2 memory references to access an address
• 2x slowdown. Bad!

11
Paging Addressing

• 32 bits VA, 4 KB frames
• 0x 00004010 ? 0000 7010
• 0x 00003010 ? 0000 D010
• 0x 00002010 ? X
• 0x 00000010 ? 0001 0010

20
16
page table base
4
12
2
4
0
8
0
4
0
12
SegmentationPaging

• Goal
• Make page table small
• More efficient support for sparse address spaces
• Ex For 20-bits page number, no need to create
  220 entries
• Idea
• Divide address space into segments (code, heap,
  stack)
• Segments can be of variable length ? add base and
  bounds
• Divide each segment into fixed-sized pages
• Implementation
• A process maintains a segment table
• Each segment has a page table
• If a process has 3 segments, it has 3 page tables
• Each segment tracks base and bounds
• Base the base address of the page table
• Bounds number of PTEs allowed to be accessed in
  this page table

13
SegmentationPaging

• Addressing
• Logical address divided into three portions
• Top-4 bits for indexing the segment table (can
  index upto 16 segments)
• Low-12 bits for page offset (a page is 4 KB then)
• Middle-16 bits for indexing the page table
• Top-4 bits (segment )
• Used to index the segment table
• Get the segment entry (get the base and bounds)
• Base get the base address of the page table for
  this segment
• Bounds number of accessible PTEs
• Middle-16 bits (page )
• Used to index the page table (the page table is
  obtained from the Base field of the segment
  entry.
• Get the frame
• Low-12 bits (page offset)
• Concatenate the frame and the page offset to get
  the physical address

14

• Q1) Page size 4 KB
• Q2) entries in page table?
• Bounded! Depends on the segment
• For example, if OS allocate 2 KB, 8 KB, and 16 KB
  for the code, heap and stack segment. Then the
  bounds ( of accessible entries) will be 1, 2,
  and 4.
• Page table size
• Code 1 4 B 4 B
• Heap 2 4 B 8 B
• Stack 4 4 B 16 B
• Goal achieved!
• Where is the page table?
• Still in memory (because bounds could be large,
  and the PT could be large too)
• Where is the segment table?
• In memory, but gets loaded into the MMU

15
Ex SegmentationPaging

• Translate 24-bit logical to physical addresses
• Page size 4KB, 12 bits offset ..
• 4 bits segment
• 8 bits page number

4
3
2
1
VPN 0
0x 002000 (PT base)
4

• 0x 002070 read 3070
• 0x 202016 read 4016
• 0x 104c84 read x
• 0x 010424 write x
• 0x 210014 write x
• 0x 203568 read 7568

3
2
1
VPN 0
0x 001000 (PT base)
16
SegmentationPaging

• B) Job of OS when P1 is created (with code
  segment 2 KB)
• Hint think reverse
• Setting up the segment and page table
• OS allocates memory for three page tables
• OS allocates memory for a segment table (as big
  as the specified bounds)
• OS stores the base PT addresses and bounds in the
  segment table
• The segment table is stored in the P1s PCB
• The segment table is loaded into the MMU
• Setting up the code segment
• Code segment is 2 KB, only need 1 frame
• OS allocates 1 frame (say frame 5)
• setup the Code segments PT0 5

17
SegmentationPaging

• C) When process runs? (see 2 slide before)
• D) malloc(1B)?
• Almost same as (B). Give it a try.
• E) malloc(gt 8 KB)?
• Suppose 8 KB is the currently allocated space for
  the heap
• So far valid PTEs for the heap segment is 2
• Need to expand the page table
• If neighboring addresses are empty, just increase
  the bounds of the PTEs in the segment table
• If not, trouble.
• Page table must be in contiguous memory (so far)
• Hence we must relocate the whole page table
  (change the PT Base Address in the segments base
  field)
• How about if a page table becomes large (e.g. 1
  MB)? We must find 1 MB contiguous memory
• In practice, it could be hard to find such a big
  contiguous memory
• Solution Paging the page table (next lecture)
• F) How many memory accesses? 2
• Segment table is in MMU, but page table is still
  in the memory

18
SegmentationPaging

• () from Segmentation
• 1) Decrease page table size
• 2) Supports sparse address spaces
• If segment not used, not need for page table
• If some PTEs are not used, PT size is decreased
• () from Paging
• 3) No external fragmentation
• 4) Segments can grow without any reshuffling
• Can run process when some pages are swapped to
  disk (more next week)
• () from both
• 5) Increases flexibility of sharing
• Share either single page or entire segment
• Share a page ? make two PTEs point to the same
  frame
• Share a segment ? make two segments base entries
  point to the same page table

19
SegmentationPaging

• -1) Inefficient (2 memory references)
• Solution Translation Lookahead Buffer (TLB)
• -2) Large page tables
• Must allocate page tables contiguously
• More problematic with more address bits
• Solution Page the page tables