Serial Powering Scheme for Silicon Strip Detectors

1
Serial Powering Scheme for Silicon Strip
Detectors
Rutherford Appleton LaboratoryParticle Physics
Department

• Giulio Villani, Mike Tyndel, Marc Weber
• CCLRC Particle Physics Division

The authors are currently constructing the ATLAS
SCT tracker illustrative calculations are shown
for the ATLAS tracker
2
Outline of the talk
Aim
Motivation
Conventional powering scheme
Proposed powering scheme Serial Powering
Project plan
Conclusions
3
Aim of the proposal

• Investigate serial powering as viable alternative
  to independent powering
• Provide proof of principle as starting point for
  future specific designs

Benefits of Serial Powering

• Reduction of number and volume of power cables
  for silicon microstrip trackers
• Increased performance due to material reduction
• Increase in power consumption efficiency
• Cost reduction

4
Silicon detector systems

• Silicon strip and pixel detectors are
  extensively used in particle physics, space
  science, heavy-ion physics, medical imaging and
  synchrotron radiation instrumentation
• Huge detector systems with up to 200 m2 and 10 M
  channels are near completion for LHC
• Power distribution to thousands of modules with
  millions of channels in very limited space is
  extremely challenging

5
Physics motivation - SLHC tracker

• The trend to ever more powerful detectors
  continues, driven by physics examples are
  silicon trackers for Super-LHC and the ILC
• LHC event
  SLHC event
• Increase in luminosity requires similar
  increase in channels to maintain tracking
  performance
• The physics at the energy frontier is so rich
  that LHC or its luminosity upgrade SLHC will
  operate much longer than 10 years
• (Tevatron has its 20th birthday this
  year)

6
SLHC Physics Reach

• Extend LHC discovery mass reach by ? 30
• - increased reach for squark and gluino by
  ?500 GeV to 3 TeV
• - increased reach for additional heavy
  gauge bosons from ?5.3 to 6.5 TeV
• - extended sensitivity (100 GeV) to heavy
  MSSM Higgses (important for distinction of MSSM
  and SM)
• - increased quark compositeness limit
  (indirect) from 40 to 60 TeV
• Increased precision in SM and Higgs physics
• - triple gauge boson and Higgs couplings
  improved by ? 2
• Increased sensitivity to rare processes/decays
• - FNC top decays e.g. limit for t-gtqZ
  increased from 1.1 to 0.1 x 10-5
• - some sensitivity to Higgs self-coupling in
  gg-gtHH channel (hopeless at LHC !)
• - some sensitivity to strongly coupled vector
  boson systems, if no Higgs (hopeless at LHC!)

7
ATLAS SCT detector as example
Nearly 2000 more cables needed in the final
assembly
ATLAS SCT Barrel 3 at CERN (192 cables visible)
Material in radiation length

• Total power is 50 kW of which 50 are dissipated
  in cables

• Material in radiation length is dominated by
  power supply and cooling services

• Upgrades and future collider experiments will
  require even more channels and thus more
  cables, more cooling and more material

Innovative powering system design is needed
8
Conventional scheme Independent Powering
N modules are powered independently by N
constant voltage power supplies

• Define efficiency ? PM/(PM Pc)
• ? 1/(1 IMRC/VM) 1/(1x)
• x IM RC/Vm voltage drop in cable/ module
  voltage
• ? decreases with increasing IM and RC and
  with decreasing Vm

Im
Im
Im
Pc nIm2 Rc
PM n ImVm

• For ATLAS SCT R 3.5 O, V 4 V, I 1.3 A
  gt x 1.14
• Power efficiency ? 50

9
Proposed scheme Serial Powering
N modules are powered in series by one constant
current source local regulators provide supply
voltage to the modules
Im
Module 1

• ? 1/(1 IR/nV) 1/(1x/n)
• Efficiency increases if number of modules n
  increases

Power cable
I Supply
Module 2

• Concept never practically implemented

Power cable
Module n
Im
Pc Im2Rc
PM nImVm

• For ATLAS SCT R 3.5 O, V 4 V, I 1.3 A N
  10 gt x 1.14
• Power efficiency ? 90

10
Advantages of serial powering

• Much less power cables
• Much less material (less cables, less cooling)
• Improved power efficiency
• Significant cost savings

11
Much less cables

• for a detector with N modules with local
  regulators, the number of cables is reduced by a
  factor of up to 2N (analogue and digital power no
  longer separated)

• Reduction of detector material in the tracking
  volume less multiple scattering and creation of
  secondary particles, leading to improved track
  finding efficiency and resolution

• Cable volume reduction is mandatory for an SLHC
  tracker, where increased luminosity would require
  an increased detectors granularity by a factor of
  5 to 10. It is even challenging to squeeze the
  current number of cables in the available space

12
Improved power efficiency

• Future readout chips require reduced
• operation voltage (due to reduced feature
• size) x increases

X 4.5
SLHC

• Overall efficiency increases with increasing
  number of modules N

X 1.14
SCT

• For a future SLHC detector x 4.5

• Independent powering ? 18
• Serial powering (n 10) ? 69
• Serial powering (n 20) ? 81

Efficiency of serial powering normalized to
independent powering vs. number of modules n for
various x factors

• Reduction of load to cooling system by tens of
  kW inside the tracker volume are possible

13
Cost savings

• Reduced number of cables and remote power
  supplies results in major cost savings
  electricity bill is reduced as well.

• Take ATLAS SCT as an example 4088 power
  supply modules cost 1.5 MCHF Cabling cost
  2 MCHF

• For an SLHC tracker with independent powering,
  the power supplies and cables would cost tens of
  MCHF a serial powering approach would reduce
  this by a large factor, implying a saving of many
  MCHF

14
Project description

• Tests with ATLAS SCT modules
• Grounding and interference issues in a realistic
  densely-packed
• detector system
• Development of a redundancy and failure
  protection scheme
• Serial Powering circuitry integration

Noise occupancy with 1 fC discriminator threshold
for standard (left) and serial (right) power
scheme. No added noise introduced by the
alternative scheme is seen.
15
Test with ATLAS SCT modules

• Detailed set of reference measurements with up to
  6 modules
• Measure power saving and compare with predicted
  values
• Noise spectrum study introduce high frequency
  noise
• Deadtime-less operation

• To gain first hands-on understanding with serial
  powering, we built a simple test system using
  existing DAQ and 4 ATLAS SCT silicon modules
  system is operating stably no evidence of
  performances degradation is yet seen

Current source
SP1
SCT1
SP2
SCT2
SP3
SCT3
SP4
SCT4
Average noise occupancies measured for four ATLAS
SCT modules (top and bottom sensor average)
Photograph of test setup with 4 ATLAS SCT
modules, serial powering scheme implemented on
PCB.
Noise occupancy with 1 fC discriminator threshold
for standard (left) and serial (right) power
scheme. No added noise introduced by the
alternative scheme is seen.
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Grounding and interference in a densely- packed
detector system

• Tests with independent modules are sensitive to
  pick-up through the
• serial power line (conductive interference)
• In an integrated detector arrangement, there are
  additional pick-up mechanisms
• e.g. capacitive and inductive interference
  between nearby components
• (bus cable/hybrids/sensors)
• We will investigate, understand and eliminate
  these by using a CDF Run IIb type stave

• This stave is a most compact package and thus
  the ultimate test bed
• Its electrical performance and interference
  mechanisms are well-understood and documented
• A stave of this kind will be available to us for
  free

CDF Run IIb stave
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Status of stave construction

• A stave will be built by Carl Haber at LBNL
• Serial powering will be added in a second step

Silicon strip stave for serial powering
implementation. Each stave is 66 cm long and
consists of 6 modules

• Stave will be available by the end of February
  2006
• mechanical tools and stave core is available
• sensors are available
• beryllia hybrids are produced and performing
  well (this is the only critical component)
• stave bus cable design finished

Hybrid with ABCD chips and test PCB
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Implementation of serial powering

• To implement serial powering, we will
• Design prototype PCB
• Assembly and test of prototype
• Design final PCB with redundancy
• Assemble and test final PCB
• Reference stave measurement
• Evaluate serial powered stave

Sensor
Serial powering PCB
Hybrid
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Redundancy and failure protection scheme

• Individual ASIC or module short circuit does not
  pose any problem with serial powering, as the
  main current loop is not interrupted
• Noisy ASICs will be treated by creating a
  controlled short in the regulator
• Open circuit within a module can be avoided by
  having parallel regulators and readout ASICS
• Open circuit between modules can be avoided by
  careful engineering e.g. parallel paths

Module n
Module n-1
Module 1
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Redundancy and failure protection scheme
SH shunt regulator
SR series regulator
Sd shunt sensing
Module n
Sa series sensing
A analog load
RDIC (1,n)
RDIC (m,n)
D digital load

• BW failure handled with current leads redundancy

Module n-1

• Power supplies redundancy each RDIC implements
  shunt and series regulator

RDIC (m,n-1)
RDIC (1,n-1)

• m RDIC in parallel (m depends on Zo of SR)

Module 1
RDIC (m,1)
RDIC (1,1)
Local power supplies option schematic diagram
to be implemented on PCB
21
Serial Powering circuitry integration

• We will perform noise tests with bare-die
  commercial regulators
• Final implementation requires radiation-hard
  ASICs
• Design, layout and fabrication of such ASICs is
  beyond scope of this proposal
• Our noise and redundancy studies will, however,
  lead to regulator specifications for a dedicated
  ASIC or a silicon strip readout chip (RDIC)
• output impedance of regulators, max. current
• PSRR of RDIC
• current sensing features of RDIC/regulators
• controlled short
• voltage adjustment features
• Design of an RDIC with serial powering features
  is discussed with CERN MIC group in the context
  of the proposed ABC-Next chip, a 0.25 µm CMOS
  RDIC

22
Project plan and milestones
Total project duration 16 months
23
Project costs and expenses

• PCB design 12 k PCB design will be
  required at each stage of the project. Four to
  six layers will be required for stave
  implementation
• PCB fabrication and population 3 k
• Component costs
  8 k
• Mostly commercial components the LBNL stave will
  require bare die ICs
• Test equipment
  4 k
• Function generator, power supply, multi-meter
• Two visiting students 3 k
• Arrival date January 9 2006
• Travel costs
  10 k
• Travel to US to help implement serial powering on
  stave and test it travel to CERN for meetings
  with MIC engineers Conference presentations
• Total request (excluding staff effort) 40 k

24
Project summary

• Serial powering offers the prospect of
  drastically reducing cable volume, cost and
  material for large-scale silicon-tracker systems
• Novel power distribution scheme is a necessity
  for SLHC trackers, but will be attractive for
  other experiments as well
• Proof of principle requires thorough
  investigation of
• Noise immunity in realistic densely-packaged
  system
• Analysis of failure modes and protection and
  redundancy schemes
• Aim of this proposal is to address above issues
  in a systematic manner
• Results must be available before SLHC tracker
  design is started

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Appendix - connection diagram -

• Serial Powering reduces the number of power
  cables by up to 2n, instead of n,
• when analogue module power is obtained from
  digital power.
• The final number of modules n will depend on
  several factors e.g. maximum allowed voltage,
  failure probability, readout architecture and
  mechanical considerations.
• The rapidly shrinking feature size in
  microelectronics, implies a decrease in x
• We thus expect the number of modules powered in
  series to be higher than 10.

The maximum voltage difference depends on the
voltage required by each module. The latter is
expected to be of the order of 1.2 2.5V maximum
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Appendix - TX/RX diagram -

• Modules are referenced to different ground
  levels than DAQ
• Modules have to send data signals to DAQ and
  receive clock and command signals from DAQ
• This is achieved by AC-coupling of LVDS signals

Figure A1 Simplified TX/RX connection diagram.
The connections are differential. Termination and
feed-back resistors are omitted for clarity.
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Appendix - Redundancy schemes -
Figure A2.1 Analogue load failure shorted to
ground
An overcurrent condition is detected by Sa
Sa turns off SR
The shared current increases by IA / n
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Appendix - Redundancy schemes -
Figure A3.2 Excess overcurrent condition
An excess overcurrent condition as a result of
broken loads or supplies
Sd lowers the voltage across the module, to
decrease power dissipated
An external supervisor chip option is also under
investigation ( to allow random turning off of
noisy sections within each module for instance)
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Appendix - Efficiency -
Efficiency analysis assuming a non uniform
current taken by each module along a chain
a max. difference in current taken by any module
with respect to the max. current
aIdm
Idm
Figure A4 Example of ratio of efficiency plot
vs. number of modules (N) for Rc 1,3 O Im
2A, a 0.75
30
Appendix - Power consumption in power cables-
Figure A5 Consumption in power cables

• one-way cable length from power supply to
  detector up to 160 m
• cable resistance (including return) 3.5 O
  1.5 O in active volume

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Appendix - Material overhead -
Figure A6 Generic tracker layout with barrel and
discs
Figure A7 Material in radiation length

• in ATLAS SCT, particles cross ?(0.1 to 0.45) x
  v2 of R.L. of cables in service gap alone (dep.
  on polar angle)
• a ten-fold increase of cables is prohibitive
• Reduction of detector material in the tracking
  volume less multiple scattering and creation of
  secondary particles, leading to improved tracking
  efficiency and resolution

32
Supermodule

• highly integrated mechanical, electrical and
  thermal structure
• single-sided silicon strip sensors on top and
  bottom 66 cm long 3072 channels low mass 150
  g 1.7 of a radiation length

33
Schematic side view

• simple layer structure SVX4 chip on BeO
  hybrid on single-sided sensor on bus cable on
  carbon fiber/foam core
• hybrid is wire-bonded to bus cable through 3 mm
  gap between pairs of sensors
• bus cable copper traces stop after reaching 3.
  hybrid
• 25/50 µm thick aluminum shields under each sensor
  pair,
• connected to hybrid ground (AGDGHG)
• top and bottom side nearly symmetric, but
  typically axial strips on top and 1.2? stereo
  strips on bottom

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Transverse cross section

• single-sided sensors
• carbon fiber/foam core
• bus cable

Supermodule cooling

• Total heat budget 18 W
• heat due to SVX4 chip 10 W
• integrated 0.1 mm thick PEEK
• cooling tubes
• coolant water/ethylene glycol (43)
• mix at -15 ?C (input)
• average strip temperature ? -10 ?C