Tests at Vienna

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FADC progress in Vienna
Reported by H.Ishino for Vienna FADC
group M.Pernicka and H.Steininger
2
Tests at ViennaY.Ushiroda (KEK) H.Ishino
(T.I.T.)

• Data transfer from FADC to PPCI
• Tests for cable cross talk
• Other topics related with FADC

3
Data transfer from FADC to PPCI

• The data transfer was successfully done with the
  10MHz clock.
• However, with 20MHz we had a problem.
• The first 32 bit datum which has a start bit was
  dropped, because the PPCI board needs 80nsec to
  be ready for receiving data.
• To solve the problem, we dropped the first clock
  signal.
• Data are transferred successfully. (we performed
  a long time test for about 12 hours. No error was
  detected.)
• This may be a potential problem, i.e. a big
  external noise would cause read out error under
  real situation.

4
100nsec
10MHz clock
Data
80nsec
XVALID (FADC asserts)
50nsec
20MHz clock
Data
This datum is not valid
5
Read out test with a pulse generator
trigger (1kHz)
TTM
ADC start
FADC board
Signal input
A pulse generator
10bit FADC
data
PC (Linux7.1)
6
Read out test with a pulse generator was
successfully done.
7
Checks for cross talk between twisted 30m cables
Single shield
Pair shield
5MHz clock signals
One of twisted cables
The other of the twisted cables
Double shield
No shield
Differential of the twisted cables
No cross talk was detected
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12
FADC status
The present Data format
32 bits
0th
ADC 10 bits
ADC 10 bits
1
0
0
1
128/ch
ADC 10 bits
1
127th
ADC 10 bits
0
0
1
Upper half part of FADC
Lower half part of FADC
Event counter from TTM (4 bits)
We need not duplicate EV counter, start/stop bit.
We requested to Vienna group to replace the one
of EV and start/stop bit to channel (4bit) and
parity bit.
Start bit (1 bit)
Stop bit (1 bit)
13
FADC status
The Data format we request
32 bits
0th
ADC 10 bits
ADC 10 bits
1
0
128/ch
ADC 10 bits
1
127th
ADC 10 bits
0
0
1
Upper half part of FADC
Lower half part of FADC
Channel (4 bits)
Event counter from TTM (4 bits)
Start bit (1 bit)
Parity bit (1 bit)
Stop bit (1 bit)
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L0 trigger
L0 processor (Altera chip) was already mounted on
a FADC board. The program which decides trigger
issue by looking at combinations of TA outputs is
being developed. If L0 processor issue trigger, a
50nsec width NIM signal and a 120nsec width ECL
signal are generated.
By Karawatzki-san (Vienna)
15
How the L1.5 trigger is implemented (outside of
FADC)
We need information of pedestal and noise levels
to set a threshold level. Those levels are
obtained from a sparcification process running on
a PC which collects raw data from FADC boards.
Write threshold levels to registers via VME bus
FADC boards
Raw data
PC (Linux)
Sparcification process
Reduce data size and calculate noise and pedestal
NSM (Network Shared Memory)
Sparc board (CPU50?)
16
How often should we update the threshold levels?
Right figures are time variations of noise and
pedestal during a run (run57, exp.17).
pedestal
noise
Noise decreases by about 6, while pedestal is
almost stable.
If we require 5 precision, we need to update the
thr. Level one or two times during a run.
This estimation came from SVD1.4. Of course the
situation of SVD2.0 would be different.
By Takeshita san (Osaka U)
17
Schedule of FADC
Vienna group will send their system (FADC board,
back board, VME crate and power supply) to KEK on
middle of Mar. The full production of FADC boards
will start on the end of April and finish on the
end of July(?).
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L1.5 trigger (inside of FADC)
Registers for a threshold level of each channel
have been prepared already. Reading/writing data
from/to the registers via VME bus using a sparc
CPU board was successfully done.
The output signal of L1.5 trigger
I am not sure for further more details about
cable connection and so on.
Ch 1
Ch 2
50nsec delay
Ch 3
100nsec delay
Ch 4
150nsec delay
50nsec
L1.5 output
20MHz clock