Design Methodology

1
Module Generation Ben Coates David
Wang Professor Brodersen BWRC Winter
retreat January 2000
2

• What is Module Generate for?
• Translates Simulinks fundamental blocks into
  real transistor layout and creates spice netlist.
• Why is so special?
• It provides a perfect match, to the bit, between
  a simulink design and a real transistor layout,
  so functionality can be assured.

3
How does it work?
A simulink designer is limited to a fundamental
library to build a design, which contains
Adder, Subtractor, Adder/Sub,Compare ,Variable
Shifter, Multiplier, Negate. Each fundamental
block has prewritten skill code (Cadence)
which takes the input and output sizes which have
been specified in Simulink as the
arguments. Then Rhetts magic program calls on
the skill code with the proper augments to build
each necessary block for the design within
Cadence- both layout and schematic.
4
Design Example Adder

• Simulink specifies an Adder with the following
  parameters
• in1 (1 4 1)
• in2 (1 5 -1)
• out1 (1 7 3 Floor 0)

This tells us to make Input A -Signed integer,
have 4 bits total, 1 data bit on the left of
decimal point, not including sign bit. Input B
-Signed integer, have 5 total bit, -1 data bits
on the left of decimal point- this actually
means the data bits will be 1 in from the right
of the decimal point. Output Z -Signed, 7 total
bits, 3 of left, round to floor, and Saturate
5
Resulting problem
A3
A2
A1
A0
B4
B3
B2
B1
B0
Z2
Z1
Z0
Z3
Z4
Z5
Z6
Zero B
A Sign of B
A B
Sign of A Sign of B
We can not just tile normal full adders for we
are not just adding inputs, we are also adding
things such as zeros and signs extensions of the
inputs We break it up into four parts
6
Available Leaf cells for Adder Add ASign BSign
Onein ABZExt
Normal full adder with inputs A and B
Adds input A to the B input of the prior adder
(Sign extension)
Adds input B to the A input of the prior adder
(Sign extension)
Adds One input (A or B) to Zero (buffer)
Adds the inputs A and B ofthe prior adder (if
output Z extends more then both inputs)
7
Which leaf cells and where?

• First section (most left) use ABZExt, because the
  output extents more then both inputs. It adds the
  sign of A to the sign of B for the first two
  spots.
• Next section we are adding A to the extended sign
  of B, so
• we will use Asign.
• Moving on to the right, we have the numbers over
  lapping, so
• we will use Add.
• The lasts section consist of only input B being
  added to nothing (zero), here we will use OneIn.

8
Finished layout
ABZExtEnd
ASign
Add
OneIn-(x3)
Add0
ABZExt
ASign
9
Whats next for Module Generation?

• Add features that characterize a module, so
  designer will know
• what they are dealing with before it is used
• Timing - speed for a given voltage and process
• Power consumption
• Size
• input capacitance