The New Low Noise Control System For The VIRGO Suspensions

1
The New Low Noise Control System For The VIRGO
Suspensions

• Alberto Gennai
• The VIRGO Collaboration

2
Digital Feedback Design in VIRGO

• Classical Design Methods
• Discrete-time controllers derived from
  continuous-time controllers (indirect design
  techniques)
• Design a continuous-time controller and then
  obtain the corresponding discrete-time controller
  using a bilinear transformation from G(s) to
  G(z).
• SISO Systems (when MIMO, systems are
  diagonalized)
• Nyquist techniques (design based on frequency
  response)

3
VIRGO Suspension Control Unit

• 2 x Motorola PowerPC-based CPU boards
• 2 x Motorola DSP96002-based boards
• 60 Analog I/O channels
• 4 Digital optical point-to-point links
• CCD Camera Interface

• 10 kHz Sampling
• 16 (14.5 eff.) bits ADC
• 20 (17.5 eff.) bits DAC
• About 90 poles for each DSP
• Floating Point Single Extended Precision (40
  bits)
• Biquad sections are implemented using first order
  filters with complex coefficients, this allowing
  a better precision on poles/zeros locations and
  much better performances from the numerical
  round-off noise.

4
VIRGO DSP Application Process View
5
Timing And Time Delay (I)

• Basic timing sequence time delay ? TS

• VIRGO DSP timing sequence time delay ? 2 TS

6
Timing And Time Delay (II)

• Total Delay Contributions
• Sampling Period
• ADC and DAC conversion time
• Processing Time
• ISR latency and context switch time
• DAC Hold Time 0.5 TS
• Anti-Aliasing and Reconstruction Filters
• Total Delay (Local Control)
• T 2 Ts 0.5 TS 4 TS 6.5 Ts (TS
  100 ?sec)
• For Global Control we need one additional TS for
  GC processing

7
VIRGO DSP

• About 80 usecs available for computation
• 8 poles 8 zeros 1 usec
• Current limits
• Total number of variables total number of
  filters coefficients cannot exceed 512 (128 var
  384 coeff). In terms of number of singularities
  we have a maximum of 128 poles 128 zeros that
  can be extended up to 192 poles and 192 zeros
  allowing some additional computation time.
• This limit was reached and big efforts are now
  needed in code optimization
• Computation Time close to limit for DSP
  controlling suspension top stage.
• I/O Limited number of I/O channels (40)
• Limit reached and influencing some architectural
  choice.
• DSP processor obsolete

8
DSP Code Example MC Local Control

• On top of already quite complex algorithms, new
  functionalities were added
• Mirror position memory
• Automatic re-lock

9
DSP Usage (08-2005)
10
New Control System

• Scope
• Upgrade of the main control loops of Virgo
  (suspensions, injection, locking and alignment)
  aiming to faster and higher dynamical range
  control systems.
• Motivations
• The control system currently in use is operative
  since 1998 (project started in 1994) and it is
  now approaching its limits in terms of
  performances for available computational power,
  converters dynamical range and components
  availability.
• The new control system foresees multi-DSP
  computing units, faster and higher resolution
  analog-to-digital and digital-to-analog
  converters and high dynamic power driver for
  coil-magnet pair actuators.

11
Running activities and development plan

• New Signal Processing Board
• Design completed in October 2004
• First prototype currently under test (September
  2005)
• New Coil-Driver
• Prototypes currently installed at VIRGO terminal
  towers and beam splitter tower.
• Final design completed January 2005
• First production and installation in 2006
• New Digital to Analog Converter Board
• Early design phase
• Software Development
• Preliminary design phase for both DSP compiler
  and top level control software

12
Multiprocessor DSP Board Main Features

• 6 x 100 MHz ADSP211160N SHARC DSP
• 3.4 GigaFLOPS in single PMC Mezzanine
• 1800 MB/s of low latency inter processor
  communication bandwidth
• 512 MB SDRAM, 4 MB ZBT SRAM, 4Mbit FLASH EPROM
• 64-bit 66 MHz PCI bus ready
• Up to 2 x PC/104-Plus Intel Celeron 933 MHz
  modules with Fast Ethernet interface running
  Linux OS
• 1 PMC Mezzanine site for optional PowerPC or
  Pentium based CPU
• 1 PMC Mezzanine site for digital optical link and
  timing interface
• On board 32-bit Master-Slave PCI to DSP Local Bus
  bridge
• 256 kWord real Dual Port memory (PCI DSP LB)
• VME to PCI Master Slave bridge
• DSP LB to VSB bridge for I/O devices access
• 200 MB/s auxiliary I/O bandwidth
• IEEE 1149.1 JTAG Standard Test Access Port
• 2 x Altera EP1C4 Cyclone FPGA
• Advanced software support from Altera Quartus II
  suite
• VisualDSP support
• Virgo DSP compiler

13
Why 3 GFLOPS ?

• Additional computational power will allow
  implementing MIMO and adaptive controllers, with
  major advantages from the so called control
  noise point of view
• Present DSPs are overloaded by data reduction and
  processing activities that cannot be handled by
  the central VIRGO data acquisition system.
  Multiple DSPs will allow keeping on implementing
  such functionalities without loading nodes devote
  to control tasks.

14
DSP Functional Blocks Diagram
15
DSP Board Description

• ADSP 21160N DSP
• Like other SHARCs, the ADSP-21160N is a 32-bit
  processor that is optimized for high performance
  DSP applications.
• The ADSP-21160N features include an 95 MHz core,
  a 4M-bit dual-ported on-chip SRAM, an integrated
  I/O processor that supports 14 DMA channels,
  multiple internal buses to eliminate I/O
  bottlenecks, two serial ports, six link ports,
  external parallel bus, and glueless
  multiprocessing.
• The ADSP-21160N introduces Single-Instruction,
  Multiple-Data (SIMD) processing. Using two
  computational units (ADSP-2106x SHARC DSPs have
  one), the ADSP-21160N can double performance
  versus the ADSP-2106x on a range of DSP
  algorithms.
• With its SIMD computational hardware running at
  95 MHz, the ADSP-21160N can perform 570 million
  math operations per second.

16
MDSPAS Top View
17
MDSPAS Bottom View
18
MDSPAS Layout Summary

• Layout StatisticsComponents 404Nets
  838Pins 5103
• Equivalent ICs (1 pin 1/14 EIC) 364Layout
  area (sq in) 17.0Layout density (sq in/EIC)
  0.047Pin density (Pins/sq in) 300.280
• Connection StatisticsConnections 4005Manh
  Distance (inches) 2707.9Etch Length (inches)
  3836.51Number of Vias 7193

19
DSP Board First prototype under test
20
MDSPAS Lay up and vias
21
Motherboard Top
VME Connectors
22
Motherboard Bottom
PC104Plus9.5 x 9
PC104Plus9.5 x 9
VME Connectors
23
New Coil Drivers

• Power amplifiers used to drive coil-magnet pair
  actuators steering VIRGO optical elements need a
  dynamical range wider than what initially
  foreseen due to the big force impulse required to
  acquire the lock of VIRGO optical cavities.
• A new coil driver was designed using two distinct
  sections one high power section for lock
  acquisition and one low noise section for linear
  regime. The two sections are driven by two
  independent digital to analog converter channels.
  The new coil driver can supply up to 3 A during
  the lock acquisition phase with a few nA/Hz1/2 of
  noise during linear regime.
• A final version of the new coil driver will host
  three distinct sections and the possibility to
  add digital to analog converters on board to
  improve EMI/EMC

24
Overview and Motivations
Initial VIRGO setup

• Actuator noise current status

25
New Coil Driver Basic Operation

• Dynamical range extension is obtained using two
  DAC channels.
• DAC 1 is used during lock acquisition phase (3A
  current). During this phase DAC 2 is set to
  zero.
• DAC 1 is then set to zero and simultaneously DAC
  2 is activated
• Finally, high power section is disconnected from
  coil actuator
• DAC 2 noise contribution is reduced by series
  resistor (500 pA/sqrt(Hz) current noise flowing
  in the coil)

26
Preliminary Desing (Protoype)

• A prototype was developed modifying existing coil
  drivers to test theory of operation
• Control functionalities were implemented using
  external devices

27
Preliminary Desing (cont.)

• No problems were noticed during prototype
  operation (now installed at terminal and beam
  spltter mirrors) excluding ...

28
Preliminary Desing (cont.)

• ...EMC problems (not deeply investigated up today)

29
Expected performances

• de-emphasis filter with ?p 2 ? rad/sec and ?z
  60 ? rad/sec

30
New Coil Driver Block Diagram

• Sections switch
• Gain selection
• De-enphasis filtering
• Monitor configuration

31
Coil Drivers Improved EMI
10 Mb/sec digital data electrically isolated

• Sections switch
• Gain selection
• De-enphasis filtering
• Monitor configuration

32
Coil Drivers Preliminary Layout
Eurocard Module (3U)
Control
DAC / ADC (optional)
Analog Sections
33
New Digital to Analog Converter Board

• The need of a very high dynamical range for
  actuators has an impact also on digital to analog
  converter boards. The board currently in use has
  -98 dB of total harmonic distortion noise while
  newer chips are available on market with 120 dB
  thus allowing a factor 10 gain in the DAC
  dynamical range.
• Two different architectures
• Standard VME board, 16 ch. 24bits (nominal)
• Distributed system

34
New Analog to Digital Converter Board

• Operation up to 100 kSamples/sec at very high
  resolution (24 bits nominal , 20 bit equivalent)
  (LAPP Annecy)
• As for Digital-to-analog converters we are
  investigating the possibility to distribute
  converters to front-end electronics to improve
  EMI.
• 2 MSamples/sec at lower resolution (16 bits
  nominal, 14 bit equivalent).
• The goal is being able to replace any analog
  control loop with a digital one
• Laser frequency stabilization.
• Laser power stabilization.

35
Conclusions

• The new VIRGO control system, based on multi-DSP
  computing units, will allow operation up to 100
  kSamples/sec at very high resolution (16
  effective bits ADC, 20 effective bits DAC) and up
  to 2 MSamples/sec at lower resolution (14
  effective bits ADC, 16-18 effective bits DAC)
  thus allowing extending applications range.
• A first prototype of new multi-DSP board is
  currently under test in our lab.
• Installation plan is quite complex.
• Late 2006
• New DSP installation
• New DAC and coil drivers electronics for payloads
  controls
• 2007
• New ADC boards